Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102167660	1			T1	20335		T2	41595		T3	108348
all_pins[1]	102167660	1			T1	20335		T2	41595		T3	108348
all_pins[2]	102167660	1			T1	20335		T2	41595		T3	108348

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	305611525	1			T1	60787		T2	124743		T3	324664
values[0x1]	891455	1			T1	218		T2	42		T3	380
transitions[0x0=>0x1]	889116	1			T1	218		T2	42		T3	380
transitions[0x1=>0x0]	889140	1			T1	218		T2	42		T3	380

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101652979	1			T1	20117		T2	41553		T3	107968
all_pins[0]	values[0x1]	514681	1			T1	218		T2	42		T3	380
all_pins[0]	transitions[0x0=>0x1]	514663	1			T1	218		T2	42		T3	380
all_pins[0]	transitions[0x1=>0x0]	60	1			T44	5		T169	6		T125	2
all_pins[1]	values[0x0]	102167582	1			T1	20335		T2	41595		T3	108348
all_pins[1]	values[0x1]	78	1			T44	5		T169	6		T125	3
all_pins[1]	transitions[0x0=>0x1]	65	1			T44	5		T169	6		T125	2
all_pins[1]	transitions[0x1=>0x0]	376683	1			T30	233		T27	967		T25	4241
all_pins[2]	values[0x0]	101790964	1			T1	20335		T2	41595		T3	108348
all_pins[2]	values[0x1]	376696	1			T30	233		T27	967		T25	4241
all_pins[2]	transitions[0x0=>0x1]	374388	1			T30	233		T27	967		T25	4204
all_pins[2]	transitions[0x1=>0x0]	512397	1			T1	218		T2	42		T3	380