Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11311364 |
1 |
|
|
T1 |
25106 |
|
T2 |
4943 |
|
T3 |
3936 |
| auto[1] |
26603699 |
1 |
|
|
T1 |
35956 |
|
T2 |
6890 |
|
T3 |
12300 |
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| word_access |
37793083 |
1 |
|
|
T1 |
60953 |
|
T2 |
11815 |
|
T3 |
16236 |
| triple_byte_access |
40639 |
1 |
|
|
T1 |
35 |
|
T2 |
3 |
|
T15 |
31 |
| halfword_access |
40796 |
1 |
|
|
T1 |
39 |
|
T2 |
10 |
|
T15 |
44 |
| byte_access |
40545 |
1 |
|
|
T1 |
35 |
|
T2 |
5 |
|
T15 |
44 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
word_access |
11189384 |
1 |
|
|
T1 |
24997 |
|
T2 |
4925 |
|
T3 |
3936 |
| auto[0] |
triple_byte_access |
40639 |
1 |
|
|
T1 |
35 |
|
T2 |
3 |
|
T15 |
31 |
| auto[0] |
halfword_access |
40796 |
1 |
|
|
T1 |
39 |
|
T2 |
10 |
|
T15 |
44 |
| auto[0] |
byte_access |
40545 |
1 |
|
|
T1 |
35 |
|
T2 |
5 |
|
T15 |
44 |
| auto[1] |
word_access |
26603699 |
1 |
|
|
T1 |
35956 |
|
T2 |
6890 |
|
T3 |
12300 |