Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100118746	1			T1	457869		T2	300		T3	318
all_values[1]	100118746	1			T1	457869		T2	300		T3	318
all_values[2]	100118746	1			T1	457869		T2	300		T3	318

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

506852

1

T2

81

T3

86

T13

182

auto[1]

299849386

1

T1

137360

T2

819

T3

868

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298822932

1

T1

136346

T2

858

T3

918

auto[1]

1533306

1

T1

10140

T2

42

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	181041	1			T2	73		T14	19470		T4	682
all_values[0]	auto[0]	auto[1]	1998	1			T2	8		T14	30		T4	6
all_values[0]	auto[1]	auto[0]	99426603	1			T1	454489		T2	213		T3	306
all_values[0]	auto[1]	auto[1]	509104	1			T1	3380		T2	6		T3	12
all_values[1]	auto[0]	auto[0]	168400	1			T3	81		T13	181		T14	691
all_values[1]	auto[0]	auto[1]	1536	1			T3	5		T13	1		T14	10
all_values[1]	auto[1]	auto[0]	99439244	1			T1	454489		T2	286		T3	225
all_values[1]	auto[1]	auto[1]	509566	1			T1	3380		T2	14		T3	7
all_values[2]	auto[0]	auto[0]	152336	1			T14	1703		T17	1137		T90	16
all_values[2]	auto[0]	auto[1]	1541	1			T14	11		T17	2		T90	11
all_values[2]	auto[1]	auto[0]	99455308	1			T1	454489		T2	286		T3	306
all_values[2]	auto[1]	auto[1]	509561	1			T1	3380		T2	14		T3	12