Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100118746	1			T1	457869		T2	300		T3	318
all_pins[1]	100118746	1			T1	457869		T2	300		T3	318
all_pins[2]	100118746	1			T1	457869		T2	300		T3	318

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299517930	1			T1	137022		T2	894		T3	942
values[0x1]	838308	1			T1	3380		T2	6		T3	12
transitions[0x0=>0x1]	836242	1			T1	3380		T2	6		T3	12
transitions[0x1=>0x0]	836265	1			T1	3380		T2	6		T3	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99609642	1			T1	454489		T2	294		T3	306
all_pins[0]	values[0x1]	509104	1			T1	3380		T2	6		T3	12
all_pins[0]	transitions[0x0=>0x1]	509085	1			T1	3380		T2	6		T3	12
all_pins[0]	transitions[0x1=>0x0]	80	1			T14	3		T179	6		T180	4
all_pins[1]	values[0x0]	100118647	1			T1	457869		T2	300		T3	318
all_pins[1]	values[0x1]	99	1			T14	3		T179	6		T180	4
all_pins[1]	transitions[0x0=>0x1]	78	1			T14	3		T179	6		T180	4
all_pins[1]	transitions[0x1=>0x0]	329084	1			T13	405		T14	14266		T26	25
all_pins[2]	values[0x0]	99789641	1			T1	457869		T2	300		T3	318
all_pins[2]	values[0x1]	329105	1			T13	405		T14	14266		T26	25
all_pins[2]	transitions[0x0=>0x1]	327079	1			T13	404		T14	14167		T26	25
all_pins[2]	transitions[0x1=>0x0]	507101	1			T1	3380		T2	6		T3	12