Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	662	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5580	1			T13	5		T14	74		T4	2
len_601_800	12622	1			T13	12		T14	142		T4	7
len_401_600	8284	1			T13	8		T14	102		T4	2
len_201_400	16494	1			T1	251		T13	1		T14	58
len_65_200	73848	1			T1	680		T13	2		T14	29
len_min_for_xof_require_squeeze	1003	1			T1	10		T14	1		T16	10
len_keccak_block_sizes[72]	762	1			T1	5		T16	5		T36	9
len_keccak_block_sizes[104]	755	1			T1	5		T16	5		T36	9
len_keccak_block_sizes[136]	766	1			T1	5		T16	5		T36	9
len_keccak_block_sizes[144]	287	1			T1	5		T14	1		T16	5
len_keccak_block_sizes[168]	283	1			T1	5		T16	5		T197	5
len_datapath_width	14168	1			T1	5		T2	3		T3	3
len_2_63	215092	1			T1	1329		T2	6		T3	6
len_1	65	1			T25	2		T24	1		T198	2