| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 92.30 | 95.88 | 92.27 | 100.00 | 68.60 | 94.11 | 98.84 | 96.43 |
| T1060 | /workspace/coverage/default/33.kmac_test_vectors_kmac.1257358932 | May 26 02:58:21 PM PDT 24 | May 26 02:58:26 PM PDT 24 | 222334471 ps | ||
| T1061 | /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.330082343 | May 26 03:00:35 PM PDT 24 | May 26 03:00:40 PM PDT 24 | 230096698 ps | ||
| T1062 | /workspace/coverage/default/18.kmac_test_vectors_sha3_256.3756930592 | May 26 02:56:06 PM PDT 24 | May 26 03:19:17 PM PDT 24 | 17491944773 ps | ||
| T1063 | /workspace/coverage/default/34.kmac_test_vectors_shake_256.3227823858 | May 26 02:58:31 PM PDT 24 | May 26 04:07:11 PM PDT 24 | 149678542767 ps | ||
| T1064 | /workspace/coverage/default/3.kmac_test_vectors_sha3_256.4159163225 | May 26 02:54:57 PM PDT 24 | May 26 03:17:26 PM PDT 24 | 35594464743 ps | ||
| T1065 | /workspace/coverage/default/43.kmac_test_vectors_kmac.4020006696 | May 26 03:00:34 PM PDT 24 | May 26 03:00:40 PM PDT 24 | 1227328321 ps | ||
| T1066 | /workspace/coverage/default/39.kmac_test_vectors_shake_128.854864022 | May 26 02:59:37 PM PDT 24 | May 26 04:12:09 PM PDT 24 | 51339668485 ps | ||
| T1067 | /workspace/coverage/default/40.kmac_test_vectors_sha3_384.1967121868 | May 26 02:59:51 PM PDT 24 | May 26 03:21:49 PM PDT 24 | 101801786805 ps | ||
| T1068 | /workspace/coverage/default/37.kmac_alert_test.1521064719 | May 26 02:59:23 PM PDT 24 | May 26 02:59:24 PM PDT 24 | 16238179 ps | ||
| T1069 | /workspace/coverage/default/21.kmac_error.2687051062 | May 26 02:56:33 PM PDT 24 | May 26 02:58:35 PM PDT 24 | 1532439653 ps | ||
| T1070 | /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.4227413052 | May 26 02:57:12 PM PDT 24 | May 26 02:57:17 PM PDT 24 | 73447713 ps | ||
| T1071 | /workspace/coverage/default/17.kmac_test_vectors_sha3_384.561586302 | May 26 02:56:05 PM PDT 24 | May 26 03:16:54 PM PDT 24 | 59546378439 ps | ||
| T1072 | /workspace/coverage/default/10.kmac_test_vectors_shake_256.939474598 | May 26 02:55:29 PM PDT 24 | May 26 03:52:13 PM PDT 24 | 186977589358 ps | ||
| T1073 | /workspace/coverage/default/48.kmac_test_vectors_shake_128.2883684649 | May 26 03:02:19 PM PDT 24 | May 26 04:14:07 PM PDT 24 | 208954388775 ps | ||
| T1074 | /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1499425342 | May 26 02:54:49 PM PDT 24 | May 26 02:54:56 PM PDT 24 | 62779066 ps | ||
| T1075 | /workspace/coverage/default/24.kmac_alert_test.1146189942 | May 26 02:56:50 PM PDT 24 | May 26 02:56:52 PM PDT 24 | 16786563 ps | ||
| T1076 | /workspace/coverage/default/17.kmac_alert_test.1040650232 | May 26 02:56:05 PM PDT 24 | May 26 02:56:07 PM PDT 24 | 26793315 ps | ||
| T1077 | /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.3769545465 | May 26 02:55:15 PM PDT 24 | May 26 02:55:24 PM PDT 24 | 167214929 ps | ||
| T1078 | /workspace/coverage/default/33.kmac_test_vectors_sha3_512.2096670649 | May 26 02:58:21 PM PDT 24 | May 26 03:13:20 PM PDT 24 | 43314143028 ps | ||
| T1079 | /workspace/coverage/default/21.kmac_app.1469911377 | May 26 02:56:28 PM PDT 24 | May 26 02:57:59 PM PDT 24 | 2004132136 ps | ||
| T1080 | /workspace/coverage/default/9.kmac_burst_write.4191633311 | May 26 02:55:24 PM PDT 24 | May 26 02:56:27 PM PDT 24 | 9316994487 ps | ||
| T1081 | /workspace/coverage/default/30.kmac_stress_all.768103981 | May 26 02:57:47 PM PDT 24 | May 26 02:58:35 PM PDT 24 | 19197088407 ps | ||
| T1082 | /workspace/coverage/default/10.kmac_test_vectors_shake_128.1382453334 | May 26 02:55:38 PM PDT 24 | May 26 04:00:07 PM PDT 24 | 107781127882 ps | ||
| T1083 | /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1268772649 | May 26 03:01:24 PM PDT 24 | May 26 03:01:29 PM PDT 24 | 2660996763 ps | ||
| T1084 | /workspace/coverage/default/30.kmac_lc_escalation.536012735 | May 26 02:57:48 PM PDT 24 | May 26 02:57:51 PM PDT 24 | 80716312 ps | ||
| T1085 | /workspace/coverage/default/22.kmac_error.1774623378 | May 26 02:56:33 PM PDT 24 | May 26 02:57:38 PM PDT 24 | 10820554603 ps | ||
| T1086 | /workspace/coverage/default/4.kmac_mubi.1114883699 | May 26 02:55:05 PM PDT 24 | May 26 02:55:29 PM PDT 24 | 1602239046 ps | ||
| T1087 | /workspace/coverage/default/18.kmac_lc_escalation.3541542694 | May 26 02:56:14 PM PDT 24 | May 26 02:56:16 PM PDT 24 | 60668956 ps | ||
| T1088 | /workspace/coverage/default/6.kmac_test_vectors_sha3_512.560124783 | May 26 02:55:12 PM PDT 24 | May 26 03:11:21 PM PDT 24 | 329049843653 ps | ||
| T1089 | /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1945619981 | May 26 01:55:15 PM PDT 24 | May 26 01:55:17 PM PDT 24 | 16787368 ps | ||
| T125 | /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3377265241 | May 26 01:55:38 PM PDT 24 | May 26 01:55:42 PM PDT 24 | 115007065 ps | ||
| T1090 | /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2651558463 | May 26 01:55:05 PM PDT 24 | May 26 01:55:07 PM PDT 24 | 163642903 ps | ||
| T117 | /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3563084359 | May 26 01:55:17 PM PDT 24 | May 26 01:55:18 PM PDT 24 | 20089034 ps | ||
| T164 | /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1697599958 | May 26 01:55:16 PM PDT 24 | May 26 01:55:20 PM PDT 24 | 534848361 ps | ||
| T1091 | /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1405432587 | May 26 01:55:29 PM PDT 24 | May 26 01:55:32 PM PDT 24 | 96102400 ps | ||
| T98 | /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3490960642 | May 26 01:55:37 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 33812347 ps | ||
| T195 | /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2554805929 | May 26 01:55:21 PM PDT 24 | May 26 01:55:23 PM PDT 24 | 47639467 ps | ||
| T118 | /workspace/coverage/cover_reg_top/41.kmac_intr_test.2088514381 | May 26 01:55:44 PM PDT 24 | May 26 01:55:45 PM PDT 24 | 19520219 ps | ||
| T149 | /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3232808816 | May 26 01:55:20 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 537791898 ps | ||
| T119 | /workspace/coverage/cover_reg_top/49.kmac_intr_test.1042641363 | May 26 01:55:44 PM PDT 24 | May 26 01:55:46 PM PDT 24 | 35580546 ps | ||
| T150 | /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3389563734 | May 26 01:55:38 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 960105464 ps | ||
| T157 | /workspace/coverage/cover_reg_top/40.kmac_intr_test.2025572516 | May 26 01:55:47 PM PDT 24 | May 26 01:55:49 PM PDT 24 | 155590739 ps | ||
| T1092 | /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1446185927 | May 26 01:55:22 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 35225096 ps | ||
| T1093 | /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.44163023 | May 26 01:55:30 PM PDT 24 | May 26 01:55:32 PM PDT 24 | 432627479 ps | ||
| T151 | /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1860042712 | May 26 01:55:33 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 70481195 ps | ||
| T99 | /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2930190344 | May 26 01:55:23 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 58210891 ps | ||
| T100 | /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.198439827 | May 26 01:55:33 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 163628993 ps | ||
| T114 | /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2556685593 | May 26 01:55:31 PM PDT 24 | May 26 01:55:37 PM PDT 24 | 370729082 ps | ||
| T1094 | /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.23369149 | May 26 01:55:08 PM PDT 24 | May 26 01:55:10 PM PDT 24 | 36814498 ps | ||
| T109 | /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.159080284 | May 26 01:55:39 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 99359867 ps | ||
| T1095 | /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.660300841 | May 26 01:55:36 PM PDT 24 | May 26 01:55:38 PM PDT 24 | 24340022 ps | ||
| T1096 | /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2801456927 | May 26 01:55:41 PM PDT 24 | May 26 01:55:44 PM PDT 24 | 91051607 ps | ||
| T1097 | /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2690282356 | May 26 01:55:31 PM PDT 24 | May 26 01:55:33 PM PDT 24 | 90042176 ps | ||
| T1098 | /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1630971234 | May 26 01:55:06 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 972566005 ps | ||
| T1099 | /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.306334959 | May 26 01:55:22 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 531500341 ps | ||
| T1100 | /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1948961022 | May 26 01:55:15 PM PDT 24 | May 26 01:55:24 PM PDT 24 | 536400392 ps | ||
| T1101 | /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.276435920 | May 26 01:55:22 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 239445843 ps | ||
| T158 | /workspace/coverage/cover_reg_top/5.kmac_intr_test.101216626 | May 26 01:55:15 PM PDT 24 | May 26 01:55:17 PM PDT 24 | 23791370 ps | ||
| T159 | /workspace/coverage/cover_reg_top/18.kmac_intr_test.3274915003 | May 26 01:55:39 PM PDT 24 | May 26 01:55:40 PM PDT 24 | 25869259 ps | ||
| T1102 | /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3739065900 | May 26 01:55:39 PM PDT 24 | May 26 01:55:42 PM PDT 24 | 142032444 ps | ||
| T160 | /workspace/coverage/cover_reg_top/7.kmac_intr_test.91774473 | May 26 01:55:22 PM PDT 24 | May 26 01:55:24 PM PDT 24 | 40908054 ps | ||
| T161 | /workspace/coverage/cover_reg_top/19.kmac_intr_test.2556076713 | May 26 01:55:37 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 26961208 ps | ||
| T1103 | /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2483111333 | May 26 01:55:05 PM PDT 24 | May 26 01:55:10 PM PDT 24 | 408539878 ps | ||
| T101 | /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1023172918 | May 26 01:55:24 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 47221242 ps | ||
| T1104 | /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3187353443 | May 26 01:55:22 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 78228242 ps | ||
| T115 | /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3982370979 | May 26 01:55:36 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 92326609 ps | ||
| T176 | /workspace/coverage/cover_reg_top/23.kmac_intr_test.497013926 | May 26 01:55:41 PM PDT 24 | May 26 01:55:42 PM PDT 24 | 47117800 ps | ||
| T1105 | /workspace/coverage/cover_reg_top/10.kmac_intr_test.2928083452 | May 26 01:55:21 PM PDT 24 | May 26 01:55:23 PM PDT 24 | 14322844 ps | ||
| T1106 | /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.602490446 | May 26 01:55:32 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 38153351 ps | ||
| T177 | /workspace/coverage/cover_reg_top/27.kmac_intr_test.947432129 | May 26 01:55:46 PM PDT 24 | May 26 01:55:48 PM PDT 24 | 11235257 ps | ||
| T1107 | /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2949222563 | May 26 01:55:17 PM PDT 24 | May 26 01:55:20 PM PDT 24 | 373219912 ps | ||
| T1108 | /workspace/coverage/cover_reg_top/28.kmac_intr_test.1536818000 | May 26 01:55:50 PM PDT 24 | May 26 01:55:51 PM PDT 24 | 12765659 ps | ||
| T1109 | /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3068000390 | May 26 01:55:15 PM PDT 24 | May 26 01:55:19 PM PDT 24 | 145973242 ps | ||
| T1110 | /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.83863225 | May 26 01:55:38 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 37931085 ps | ||
| T139 | /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2107728042 | May 26 01:54:59 PM PDT 24 | May 26 01:55:02 PM PDT 24 | 71493698 ps | ||
| T102 | /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1815573235 | May 26 01:55:15 PM PDT 24 | May 26 01:55:19 PM PDT 24 | 50217601 ps | ||
| T1111 | /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3979896993 | May 26 01:55:23 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 47677633 ps | ||
| T1112 | /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.461099910 | May 26 01:55:22 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 130880576 ps | ||
| T178 | /workspace/coverage/cover_reg_top/3.kmac_intr_test.3491235863 | May 26 01:55:16 PM PDT 24 | May 26 01:55:18 PM PDT 24 | 12299743 ps | ||
| T1113 | /workspace/coverage/cover_reg_top/32.kmac_intr_test.2064360467 | May 26 01:55:47 PM PDT 24 | May 26 01:55:49 PM PDT 24 | 18919835 ps | ||
| T1114 | /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1072170915 | May 26 01:55:04 PM PDT 24 | May 26 01:55:07 PM PDT 24 | 94412069 ps | ||
| T1115 | /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1559912877 | May 26 01:55:20 PM PDT 24 | May 26 01:55:23 PM PDT 24 | 181635106 ps | ||
| T1116 | /workspace/coverage/cover_reg_top/22.kmac_intr_test.2043584107 | May 26 01:55:39 PM PDT 24 | May 26 01:55:40 PM PDT 24 | 116422249 ps | ||
| T116 | /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1307576364 | May 26 01:55:32 PM PDT 24 | May 26 01:55:36 PM PDT 24 | 359533828 ps | ||
| T1117 | /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3812668776 | May 26 01:54:58 PM PDT 24 | May 26 01:55:01 PM PDT 24 | 57204497 ps | ||
| T103 | /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2351924796 | May 26 01:55:20 PM PDT 24 | May 26 01:55:22 PM PDT 24 | 126788943 ps | ||
| T113 | /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2777732572 | May 26 01:55:34 PM PDT 24 | May 26 01:55:36 PM PDT 24 | 58504453 ps | ||
| T140 | /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1327999796 | May 26 01:55:08 PM PDT 24 | May 26 01:55:09 PM PDT 24 | 203594462 ps | ||
| T163 | /workspace/coverage/cover_reg_top/13.kmac_tl_errors.825132998 | May 26 01:55:33 PM PDT 24 | May 26 01:55:36 PM PDT 24 | 257347016 ps | ||
| T182 | /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.39559027 | May 26 01:55:40 PM PDT 24 | May 26 01:55:45 PM PDT 24 | 171960197 ps | ||
| T110 | /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2219716022 | May 26 01:55:37 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 176525304 ps | ||
| T152 | /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.373470332 | May 26 01:55:21 PM PDT 24 | May 26 01:55:24 PM PDT 24 | 67039959 ps | ||
| T1118 | /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3223174120 | May 26 01:55:12 PM PDT 24 | May 26 01:55:15 PM PDT 24 | 244305686 ps | ||
| T153 | /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2014698065 | May 26 01:55:15 PM PDT 24 | May 26 01:55:16 PM PDT 24 | 57571948 ps | ||
| T191 | /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.858397297 | May 26 01:55:38 PM PDT 24 | May 26 01:55:42 PM PDT 24 | 423817857 ps | ||
| T1119 | /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1363164404 | May 26 01:55:37 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 151287349 ps | ||
| T1120 | /workspace/coverage/cover_reg_top/9.kmac_csr_rw.2220110438 | May 26 01:55:22 PM PDT 24 | May 26 01:55:24 PM PDT 24 | 21584459 ps | ||
| T104 | /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4004079571 | May 26 01:55:05 PM PDT 24 | May 26 01:55:08 PM PDT 24 | 88276630 ps | ||
| T154 | /workspace/coverage/cover_reg_top/3.kmac_csr_rw.4104980377 | May 26 01:55:17 PM PDT 24 | May 26 01:55:19 PM PDT 24 | 22475640 ps | ||
| T141 | /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3165301911 | May 26 01:55:06 PM PDT 24 | May 26 01:55:08 PM PDT 24 | 123808094 ps | ||
| T1121 | /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1522432750 | May 26 01:55:13 PM PDT 24 | May 26 01:55:16 PM PDT 24 | 269898627 ps | ||
| T1122 | /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2996232037 | May 26 01:55:04 PM PDT 24 | May 26 01:55:06 PM PDT 24 | 82817058 ps | ||
| T142 | /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2557322137 | May 26 01:55:07 PM PDT 24 | May 26 01:55:09 PM PDT 24 | 17087018 ps | ||
| T108 | /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2715555323 | May 26 01:55:15 PM PDT 24 | May 26 01:55:17 PM PDT 24 | 65562001 ps | ||
| T1123 | /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.127727483 | May 26 01:55:39 PM PDT 24 | May 26 01:55:42 PM PDT 24 | 93781721 ps | ||
| T1124 | /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2778081040 | May 26 01:55:24 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 56522276 ps | ||
| T1125 | /workspace/coverage/cover_reg_top/20.kmac_intr_test.838151697 | May 26 01:55:36 PM PDT 24 | May 26 01:55:37 PM PDT 24 | 17147148 ps | ||
| T193 | /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1545040916 | May 26 01:55:42 PM PDT 24 | May 26 01:55:45 PM PDT 24 | 365090149 ps | ||
| T1126 | /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1542641095 | May 26 01:55:21 PM PDT 24 | May 26 01:55:24 PM PDT 24 | 42387667 ps | ||
| T1127 | /workspace/coverage/cover_reg_top/38.kmac_intr_test.2248836633 | May 26 01:55:46 PM PDT 24 | May 26 01:55:48 PM PDT 24 | 31166688 ps | ||
| T1128 | /workspace/coverage/cover_reg_top/37.kmac_intr_test.3113768974 | May 26 01:55:47 PM PDT 24 | May 26 01:55:49 PM PDT 24 | 13837110 ps | ||
| T1129 | /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2057344231 | May 26 01:55:06 PM PDT 24 | May 26 01:55:08 PM PDT 24 | 23725135 ps | ||
| T1130 | /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1970071728 | May 26 01:54:58 PM PDT 24 | May 26 01:55:00 PM PDT 24 | 17712432 ps | ||
| T1131 | /workspace/coverage/cover_reg_top/11.kmac_intr_test.1244091799 | May 26 01:55:31 PM PDT 24 | May 26 01:55:32 PM PDT 24 | 14668531 ps | ||
| T1132 | /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2029416892 | May 26 01:55:36 PM PDT 24 | May 26 01:55:40 PM PDT 24 | 84899991 ps | ||
| T1133 | /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.2523283043 | May 26 01:55:14 PM PDT 24 | May 26 01:55:15 PM PDT 24 | 21001514 ps | ||
| T106 | /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2859727549 | May 26 01:55:31 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 140645948 ps | ||
| T155 | /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1601805675 | May 26 01:54:59 PM PDT 24 | May 26 01:55:01 PM PDT 24 | 126727010 ps | ||
| T1134 | /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1122880197 | May 26 01:54:57 PM PDT 24 | May 26 01:54:58 PM PDT 24 | 91495062 ps | ||
| T162 | /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1132618559 | May 26 01:55:32 PM PDT 24 | May 26 01:55:34 PM PDT 24 | 78826878 ps | ||
| T1135 | /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1740683099 | May 26 01:55:33 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 31151270 ps | ||
| T105 | /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4157017820 | May 26 01:55:12 PM PDT 24 | May 26 01:55:14 PM PDT 24 | 84201789 ps | ||
| T185 | /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3053379147 | May 26 01:55:25 PM PDT 24 | May 26 01:55:30 PM PDT 24 | 330250344 ps | ||
| T1136 | /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.357336716 | May 26 01:55:24 PM PDT 24 | May 26 01:55:28 PM PDT 24 | 109942807 ps | ||
| T1137 | /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1521677427 | May 26 01:55:08 PM PDT 24 | May 26 01:55:09 PM PDT 24 | 14036219 ps | ||
| T1138 | /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1080023097 | May 26 01:55:08 PM PDT 24 | May 26 01:55:13 PM PDT 24 | 75557449 ps | ||
| T1139 | /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3482515797 | May 26 01:55:08 PM PDT 24 | May 26 01:55:12 PM PDT 24 | 473602934 ps | ||
| T1140 | /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3295767491 | May 26 01:55:12 PM PDT 24 | May 26 01:55:15 PM PDT 24 | 59304005 ps | ||
| T1141 | /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1727619395 | May 26 01:55:39 PM PDT 24 | May 26 01:55:40 PM PDT 24 | 20385431 ps | ||
| T1142 | /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2751043237 | May 26 01:55:07 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 3862470642 ps | ||
| T1143 | /workspace/coverage/cover_reg_top/45.kmac_intr_test.1624386387 | May 26 01:55:47 PM PDT 24 | May 26 01:55:49 PM PDT 24 | 46138342 ps | ||
| T1144 | /workspace/coverage/cover_reg_top/21.kmac_intr_test.1063312170 | May 26 01:55:40 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 16451969 ps | ||
| T156 | /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3825866981 | May 26 01:55:21 PM PDT 24 | May 26 01:55:24 PM PDT 24 | 296741576 ps | ||
| T1145 | /workspace/coverage/cover_reg_top/13.kmac_intr_test.1934965793 | May 26 01:55:30 PM PDT 24 | May 26 01:55:32 PM PDT 24 | 14185107 ps | ||
| T183 | /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1050490296 | May 26 01:55:30 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 733688914 ps | ||
| T1146 | /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.161409840 | May 26 01:55:39 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 21444680 ps | ||
| T1147 | /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2062086361 | May 26 01:55:12 PM PDT 24 | May 26 01:55:14 PM PDT 24 | 165308012 ps | ||
| T186 | /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2550997107 | May 26 01:55:10 PM PDT 24 | May 26 01:55:14 PM PDT 24 | 759667385 ps | ||
| T1148 | /workspace/coverage/cover_reg_top/6.kmac_intr_test.1946929157 | May 26 01:55:22 PM PDT 24 | May 26 01:55:23 PM PDT 24 | 42341446 ps | ||
| T1149 | /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2632333663 | May 26 01:55:21 PM PDT 24 | May 26 01:55:24 PM PDT 24 | 36564794 ps | ||
| T107 | /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2440917668 | May 26 01:55:07 PM PDT 24 | May 26 01:55:10 PM PDT 24 | 120809618 ps | ||
| T1150 | /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1605936653 | May 26 01:55:40 PM PDT 24 | May 26 01:55:43 PM PDT 24 | 51305038 ps | ||
| T1151 | /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2827039805 | May 26 01:55:17 PM PDT 24 | May 26 01:55:19 PM PDT 24 | 111906128 ps | ||
| T1152 | /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2320912728 | May 26 01:55:33 PM PDT 24 | May 26 01:55:36 PM PDT 24 | 95882634 ps | ||
| T1153 | /workspace/coverage/cover_reg_top/2.kmac_intr_test.437307756 | May 26 01:55:05 PM PDT 24 | May 26 01:55:07 PM PDT 24 | 15931894 ps | ||
| T1154 | /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.4192640233 | May 26 01:55:23 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 111771112 ps | ||
| T1155 | /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3714320832 | May 26 01:55:36 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 491245291 ps | ||
| T1156 | /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.487272535 | May 26 01:55:05 PM PDT 24 | May 26 01:55:06 PM PDT 24 | 17742518 ps | ||
| T1157 | /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1718204721 | May 26 01:54:58 PM PDT 24 | May 26 01:55:08 PM PDT 24 | 571126764 ps | ||
| T1158 | /workspace/coverage/cover_reg_top/47.kmac_intr_test.2953352849 | May 26 01:55:47 PM PDT 24 | May 26 01:55:49 PM PDT 24 | 22044832 ps | ||
| T1159 | /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1744342338 | May 26 01:55:23 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 98146158 ps | ||
| T1160 | /workspace/coverage/cover_reg_top/16.kmac_intr_test.2824173226 | May 26 01:55:39 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 27587697 ps | ||
| T1161 | /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.194897430 | May 26 01:55:42 PM PDT 24 | May 26 01:55:44 PM PDT 24 | 139431183 ps | ||
| T1162 | /workspace/coverage/cover_reg_top/33.kmac_intr_test.2808206549 | May 26 01:55:48 PM PDT 24 | May 26 01:55:50 PM PDT 24 | 18803073 ps | ||
| T1163 | /workspace/coverage/cover_reg_top/35.kmac_intr_test.1734497985 | May 26 01:55:45 PM PDT 24 | May 26 01:55:47 PM PDT 24 | 52394411 ps | ||
| T1164 | /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2878762902 | May 26 01:55:41 PM PDT 24 | May 26 01:55:43 PM PDT 24 | 38971024 ps | ||
| T1165 | /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2127220210 | May 26 01:55:36 PM PDT 24 | May 26 01:55:38 PM PDT 24 | 136065048 ps | ||
| T1166 | /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.657855213 | May 26 01:55:23 PM PDT 24 | May 26 01:55:27 PM PDT 24 | 455084976 ps | ||
| T1167 | /workspace/coverage/cover_reg_top/9.kmac_tl_errors.648358456 | May 26 01:55:23 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 395854818 ps | ||
| T1168 | /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2555593668 | May 26 01:55:23 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 25493665 ps | ||
| T1169 | /workspace/coverage/cover_reg_top/44.kmac_intr_test.2119060533 | May 26 01:55:48 PM PDT 24 | May 26 01:55:50 PM PDT 24 | 23737075 ps | ||
| T184 | /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1282161271 | May 26 01:55:06 PM PDT 24 | May 26 01:55:10 PM PDT 24 | 142231269 ps | ||
| T1170 | /workspace/coverage/cover_reg_top/4.kmac_csr_rw.199073430 | May 26 01:55:13 PM PDT 24 | May 26 01:55:15 PM PDT 24 | 51658061 ps | ||
| T1171 | /workspace/coverage/cover_reg_top/34.kmac_intr_test.3867247847 | May 26 01:55:44 PM PDT 24 | May 26 01:55:45 PM PDT 24 | 15726758 ps | ||
| T1172 | /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1562869378 | May 26 01:54:59 PM PDT 24 | May 26 01:55:01 PM PDT 24 | 39852151 ps | ||
| T1173 | /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3713303862 | May 26 01:55:17 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 626642876 ps | ||
| T1174 | /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3045716959 | May 26 01:55:21 PM PDT 24 | May 26 01:55:23 PM PDT 24 | 217073341 ps | ||
| T1175 | /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2574528926 | May 26 01:55:23 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 84933051 ps | ||
| T1176 | /workspace/coverage/cover_reg_top/15.kmac_tl_errors.995314677 | May 26 01:55:33 PM PDT 24 | May 26 01:55:36 PM PDT 24 | 1567615796 ps | ||
| T1177 | /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.89603918 | May 26 01:55:16 PM PDT 24 | May 26 01:55:20 PM PDT 24 | 468914721 ps | ||
| T1178 | /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.481942389 | May 26 01:55:34 PM PDT 24 | May 26 01:55:37 PM PDT 24 | 361383054 ps | ||
| T1179 | /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1839059022 | May 26 01:54:57 PM PDT 24 | May 26 01:54:59 PM PDT 24 | 94450943 ps | ||
| T1180 | /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3641774269 | May 26 01:55:37 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 196177158 ps | ||
| T1181 | /workspace/coverage/cover_reg_top/0.kmac_intr_test.278322277 | May 26 01:55:05 PM PDT 24 | May 26 01:55:07 PM PDT 24 | 19042702 ps | ||
| T187 | /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.283664534 | May 26 01:55:05 PM PDT 24 | May 26 01:55:11 PM PDT 24 | 802261908 ps | ||
| T1182 | /workspace/coverage/cover_reg_top/43.kmac_intr_test.2577125518 | May 26 01:55:45 PM PDT 24 | May 26 01:55:46 PM PDT 24 | 17075077 ps | ||
| T188 | /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3054680994 | May 26 01:55:17 PM PDT 24 | May 26 01:55:20 PM PDT 24 | 210053632 ps | ||
| T194 | /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.4214793857 | May 26 01:55:12 PM PDT 24 | May 26 01:55:15 PM PDT 24 | 105651846 ps | ||
| T1183 | /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1199323570 | May 26 01:55:08 PM PDT 24 | May 26 01:55:11 PM PDT 24 | 242512290 ps | ||
| T1184 | /workspace/coverage/cover_reg_top/8.kmac_intr_test.2706076126 | May 26 01:55:25 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 37877284 ps | ||
| T1185 | /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2117922284 | May 26 01:55:37 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 829725013 ps | ||
| T1186 | /workspace/coverage/cover_reg_top/48.kmac_intr_test.2948600390 | May 26 01:55:47 PM PDT 24 | May 26 01:55:49 PM PDT 24 | 27788400 ps | ||
| T1187 | /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2916148114 | May 26 01:55:32 PM PDT 24 | May 26 01:55:33 PM PDT 24 | 22381408 ps | ||
| T1188 | /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1263292362 | May 26 01:55:39 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 56138855 ps | ||
| T190 | /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1506761368 | May 26 01:55:20 PM PDT 24 | May 26 01:55:24 PM PDT 24 | 379950770 ps | ||
| T1189 | /workspace/coverage/cover_reg_top/42.kmac_intr_test.2729722764 | May 26 01:55:50 PM PDT 24 | May 26 01:55:51 PM PDT 24 | 41600682 ps | ||
| T1190 | /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2379831805 | May 26 01:55:34 PM PDT 24 | May 26 01:55:36 PM PDT 24 | 50013224 ps | ||
| T1191 | /workspace/coverage/cover_reg_top/25.kmac_intr_test.4077259675 | May 26 01:55:46 PM PDT 24 | May 26 01:55:48 PM PDT 24 | 16530705 ps | ||
| T1192 | /workspace/coverage/cover_reg_top/15.kmac_intr_test.3834930948 | May 26 01:55:32 PM PDT 24 | May 26 01:55:33 PM PDT 24 | 12570118 ps | ||
| T1193 | /workspace/coverage/cover_reg_top/12.kmac_intr_test.749306438 | May 26 01:55:33 PM PDT 24 | May 26 01:55:34 PM PDT 24 | 23529402 ps | ||
| T1194 | /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1259202715 | May 26 01:55:15 PM PDT 24 | May 26 01:55:19 PM PDT 24 | 194406692 ps | ||
| T1195 | /workspace/coverage/cover_reg_top/24.kmac_intr_test.3591892110 | May 26 01:55:49 PM PDT 24 | May 26 01:55:50 PM PDT 24 | 28642383 ps | ||
| T1196 | /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2459675836 | May 26 01:55:31 PM PDT 24 | May 26 01:55:32 PM PDT 24 | 232012952 ps | ||
| T1197 | /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2555300371 | May 26 01:55:31 PM PDT 24 | May 26 01:55:34 PM PDT 24 | 81473541 ps | ||
| T1198 | /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3611667905 | May 26 01:55:08 PM PDT 24 | May 26 01:55:11 PM PDT 24 | 54604845 ps | ||
| T1199 | /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3974819266 | May 26 01:55:08 PM PDT 24 | May 26 01:55:11 PM PDT 24 | 100214902 ps | ||
| T1200 | /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2021325702 | May 26 01:55:29 PM PDT 24 | May 26 01:55:30 PM PDT 24 | 31544329 ps | ||
| T1201 | /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3393997506 | May 26 01:55:29 PM PDT 24 | May 26 01:55:33 PM PDT 24 | 372922178 ps | ||
| T1202 | /workspace/coverage/cover_reg_top/39.kmac_intr_test.1885290933 | May 26 01:55:49 PM PDT 24 | May 26 01:55:50 PM PDT 24 | 15548324 ps | ||
| T1203 | /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2956324135 | May 26 01:55:34 PM PDT 24 | May 26 01:55:38 PM PDT 24 | 74273347 ps | ||
| T143 | /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.965635247 | May 26 01:55:15 PM PDT 24 | May 26 01:55:16 PM PDT 24 | 31478188 ps | ||
| T1204 | /workspace/coverage/cover_reg_top/26.kmac_intr_test.1785451204 | May 26 01:55:47 PM PDT 24 | May 26 01:55:49 PM PDT 24 | 23443638 ps | ||
| T192 | /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2896036868 | May 26 01:55:22 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 435972968 ps | ||
| T1205 | /workspace/coverage/cover_reg_top/14.kmac_intr_test.783522442 | May 26 01:55:32 PM PDT 24 | May 26 01:55:33 PM PDT 24 | 75051400 ps | ||
| T1206 | /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2019713453 | May 26 01:55:06 PM PDT 24 | May 26 01:55:16 PM PDT 24 | 157921241 ps | ||
| T1207 | /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1890876784 | May 26 01:55:11 PM PDT 24 | May 26 01:55:12 PM PDT 24 | 119895481 ps | ||
| T1208 | /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2193093438 | May 26 01:55:22 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 347611850 ps | ||
| T1209 | /workspace/coverage/cover_reg_top/11.kmac_tl_errors.4041195260 | May 26 01:55:21 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 133873661 ps | ||
| T1210 | /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.692760209 | May 26 01:55:09 PM PDT 24 | May 26 01:55:12 PM PDT 24 | 141287051 ps | ||
| T1211 | /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1796335911 | May 26 01:55:30 PM PDT 24 | May 26 01:55:32 PM PDT 24 | 41902619 ps | ||
| T1212 | /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1705743387 | May 26 01:55:17 PM PDT 24 | May 26 01:55:19 PM PDT 24 | 38826586 ps | ||
| T1213 | /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1317970186 | May 26 01:55:15 PM PDT 24 | May 26 01:55:18 PM PDT 24 | 27876792 ps | ||
| T1214 | /workspace/coverage/cover_reg_top/12.kmac_tl_errors.45608222 | May 26 01:55:32 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 43503345 ps | ||
| T1215 | /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1926760691 | May 26 01:55:02 PM PDT 24 | May 26 01:55:03 PM PDT 24 | 29873791 ps | ||
| T1216 | /workspace/coverage/cover_reg_top/1.kmac_intr_test.3322034735 | May 26 01:55:05 PM PDT 24 | May 26 01:55:07 PM PDT 24 | 15082455 ps | ||
| T1217 | /workspace/coverage/cover_reg_top/30.kmac_intr_test.2033801654 | May 26 01:55:45 PM PDT 24 | May 26 01:55:46 PM PDT 24 | 38160679 ps | ||
| T1218 | /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.537173374 | May 26 01:55:24 PM PDT 24 | May 26 01:55:27 PM PDT 24 | 604906270 ps | ||
| T1219 | /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3204679278 | May 26 01:55:16 PM PDT 24 | May 26 01:55:25 PM PDT 24 | 154701081 ps | ||
| T1220 | /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1744313721 | May 26 01:55:23 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 199941722 ps | ||
| T1221 | /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2771539227 | May 26 01:55:12 PM PDT 24 | May 26 01:55:14 PM PDT 24 | 22507258 ps | ||
| T1222 | /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2404948675 | May 26 01:55:15 PM PDT 24 | May 26 01:55:19 PM PDT 24 | 143954321 ps | ||
| T1223 | /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3506139798 | May 26 01:55:40 PM PDT 24 | May 26 01:55:43 PM PDT 24 | 69056665 ps | ||
| T1224 | /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1757209659 | May 26 01:55:01 PM PDT 24 | May 26 01:55:04 PM PDT 24 | 130094925 ps | ||
| T1225 | /workspace/coverage/cover_reg_top/17.kmac_intr_test.3121951575 | May 26 01:55:37 PM PDT 24 | May 26 01:55:39 PM PDT 24 | 18339851 ps | ||
| T1226 | /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.512354499 | May 26 01:55:32 PM PDT 24 | May 26 01:55:35 PM PDT 24 | 220958566 ps | ||
| T1227 | /workspace/coverage/cover_reg_top/29.kmac_intr_test.2262181884 | May 26 01:55:45 PM PDT 24 | May 26 01:55:46 PM PDT 24 | 143549355 ps | ||
| T1228 | /workspace/coverage/cover_reg_top/9.kmac_intr_test.2327412169 | May 26 01:55:21 PM PDT 24 | May 26 01:55:23 PM PDT 24 | 37304982 ps | ||
| T1229 | /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.393811860 | May 26 01:55:38 PM PDT 24 | May 26 01:55:40 PM PDT 24 | 16652471 ps | ||
| T1230 | /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1279778060 | May 26 01:55:39 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 28626541 ps | ||
| T1231 | /workspace/coverage/cover_reg_top/31.kmac_intr_test.4227664347 | May 26 01:55:51 PM PDT 24 | May 26 01:55:52 PM PDT 24 | 50935954 ps | ||
| T1232 | /workspace/coverage/cover_reg_top/36.kmac_intr_test.1117086673 | May 26 01:55:46 PM PDT 24 | May 26 01:55:48 PM PDT 24 | 71267481 ps | ||
| T1233 | /workspace/coverage/cover_reg_top/6.kmac_csr_rw.2303758827 | May 26 01:55:21 PM PDT 24 | May 26 01:55:22 PM PDT 24 | 22530304 ps | ||
| T1234 | /workspace/coverage/cover_reg_top/2.kmac_csr_rw.3068796014 | May 26 01:55:06 PM PDT 24 | May 26 01:55:08 PM PDT 24 | 95307463 ps | ||
| T1235 | /workspace/coverage/cover_reg_top/46.kmac_intr_test.1329627199 | May 26 01:55:46 PM PDT 24 | May 26 01:55:48 PM PDT 24 | 64725769 ps | ||
| T189 | /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.615286971 | May 26 01:55:20 PM PDT 24 | May 26 01:55:26 PM PDT 24 | 252206910 ps | ||
| T1236 | /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2991045930 | May 26 01:55:39 PM PDT 24 | May 26 01:55:41 PM PDT 24 | 47048447 ps | ||
| T1237 | /workspace/coverage/cover_reg_top/4.kmac_intr_test.1400334465 | May 26 01:55:15 PM PDT 24 | May 26 01:55:16 PM PDT 24 | 36369214 ps |
| Test location | /workspace/coverage/default/32.kmac_stress_all.427413505 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 61841411155 ps |
| CPU time | 1763.66 seconds |
| Started | May 26 02:58:13 PM PDT 24 |
| Finished | May 26 03:27:38 PM PDT 24 |
| Peak memory | 435452 kb |
| Host | smart-3a2bbd00-54ac-4def-83e3-33c3f516fea4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=427413505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.427413505 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2556685593 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 370729082 ps |
| CPU time | 4.67 seconds |
| Started | May 26 01:55:31 PM PDT 24 |
| Finished | May 26 01:55:37 PM PDT 24 |
| Peak memory | 214904 kb |
| Host | smart-039bf16c-0d4d-479f-a13c-af9d9faa0f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556685593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2556 685593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/default/4.kmac_sec_cm.582714001 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4559507655 ps |
| CPU time | 55.62 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:56:12 PM PDT 24 |
| Peak memory | 268288 kb |
| Host | smart-e21a52e2-0fdd-410b-8720-040cc584023e |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582714001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.582714001 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_sec_cm/latest |
| Test location | /workspace/coverage/default/35.kmac_stress_all_with_rand_reset.4107463561 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 205772874910 ps |
| CPU time | 3369.09 seconds |
| Started | May 26 02:58:52 PM PDT 24 |
| Finished | May 26 03:55:03 PM PDT 24 |
| Peak memory | 541840 kb |
| Host | smart-6820e4d7-a0e0-4cf8-a77b-349d1602c427 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4107463561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all_with_rand_reset.4107463561 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.kmac_test_vectors_shake_256.2714242238 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 694375939460 ps |
| CPU time | 4331.05 seconds |
| Started | May 26 02:55:22 PM PDT 24 |
| Finished | May 26 04:07:35 PM PDT 24 |
| Peak memory | 557652 kb |
| Host | smart-d51b11d7-2124-4ca6-bb0a-ca6973a2ef71 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2714242238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.2714242238 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/47.kmac_key_error.896497011 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3313969611 ps |
| CPU time | 9.36 seconds |
| Started | May 26 03:01:47 PM PDT 24 |
| Finished | May 26 03:01:56 PM PDT 24 |
| Peak memory | 207156 kb |
| Host | smart-5ca918ac-aa49-41c2-9565-4e7965cabd6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=896497011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.896497011 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_key_error/latest |
| Test location | /workspace/coverage/default/45.kmac_lc_escalation.3157474202 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 263654716 ps |
| CPU time | 1.41 seconds |
| Started | May 26 03:01:08 PM PDT 24 |
| Finished | May 26 03:01:10 PM PDT 24 |
| Peak memory | 215368 kb |
| Host | smart-3b5b8fce-972a-4a7c-ab6b-e7749135b690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157474202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3157474202 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/45.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/2.kmac_error.3450081696 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 20594271070 ps |
| CPU time | 388.45 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 03:01:33 PM PDT 24 |
| Peak memory | 269348 kb |
| Host | smart-b35ca43c-2c4f-4ac1-b24e-d238b2217b15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450081696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3450081696 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2859727549 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 140645948 ps |
| CPU time | 2.82 seconds |
| Started | May 26 01:55:31 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 215428 kb |
| Host | smart-cd9df0e7-eed5-4952-9581-50afbdb6868a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859727549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.2859727549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/default/33.kmac_lc_escalation.945953499 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7082410420 ps |
| CPU time | 45.14 seconds |
| Started | May 26 02:58:30 PM PDT 24 |
| Finished | May 26 02:59:16 PM PDT 24 |
| Peak memory | 232268 kb |
| Host | smart-0b014cb2-fe12-43db-8faf-298b237fc3ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945953499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.945953499 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/33.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/3.kmac_lc_escalation.605071525 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 108616234 ps |
| CPU time | 2.9 seconds |
| Started | May 26 02:55:03 PM PDT 24 |
| Finished | May 26 02:55:09 PM PDT 24 |
| Peak memory | 220984 kb |
| Host | smart-d8794ad8-ef9e-4198-9a22-42a687aed63e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=605071525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.605071525 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/40.kmac_intr_test.2025572516 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 155590739 ps |
| CPU time | 0.79 seconds |
| Started | May 26 01:55:47 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 206452 kb |
| Host | smart-176e08b5-00a4-4a2d-9a89-a3e06d5b9e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025572516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2025572516 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_intr_test/latest |
| Test location | /workspace/coverage/default/1.kmac_lc_escalation.3944427395 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 58371907 ps |
| CPU time | 1.32 seconds |
| Started | May 26 02:54:51 PM PDT 24 |
| Finished | May 26 02:54:55 PM PDT 24 |
| Peak memory | 219716 kb |
| Host | smart-38c81de3-dc81-434b-9a80-f305734dcba9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944427395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3944427395 +enable_masking=0 +sw_ke y_masked=0 |
| Directory | /workspace/1.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4157017820 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 84201789 ps |
| CPU time | 1.33 seconds |
| Started | May 26 01:55:12 PM PDT 24 |
| Finished | May 26 01:55:14 PM PDT 24 |
| Peak memory | 215492 kb |
| Host | smart-a85ab3d0-ff1b-4677-9b6b-25cc093d6191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157017820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.4157017820 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/default/11.kmac_alert_test.239946051 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 166936797 ps |
| CPU time | 0.8 seconds |
| Started | May 26 02:55:41 PM PDT 24 |
| Finished | May 26 02:55:43 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-99f60271-c016-4155-90c7-6f3112dee7a0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239946051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.239946051 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2557322137 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 17087018 ps |
| CPU time | 1.16 seconds |
| Started | May 26 01:55:07 PM PDT 24 |
| Finished | May 26 01:55:09 PM PDT 24 |
| Peak memory | 214860 kb |
| Host | smart-f831bdff-0613-4c54-84d7-102922001e7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557322137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.2557322137 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/19.kmac_intr_test.2556076713 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 26961208 ps |
| CPU time | 0.83 seconds |
| Started | May 26 01:55:37 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 206568 kb |
| Host | smart-cddc4aa3-652e-4d6c-b82b-000961d13de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556076713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2556076713 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3982370979 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 92326609 ps |
| CPU time | 2.32 seconds |
| Started | May 26 01:55:36 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 214956 kb |
| Host | smart-06450ca4-c278-461c-b99a-91c20125e94f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982370979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3982 370979 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.357336716 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 109942807 ps |
| CPU time | 2.67 seconds |
| Started | May 26 01:55:24 PM PDT 24 |
| Finished | May 26 01:55:28 PM PDT 24 |
| Peak memory | 215484 kb |
| Host | smart-4525d97d-c4db-441c-ba8e-4c664a08bcc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357336716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac _shadow_reg_errors_with_csr_rw.357336716 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/default/3.kmac_entropy_ready_error.2695957292 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4387900374 ps |
| CPU time | 41.35 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 02:55:45 PM PDT 24 |
| Peak memory | 216272 kb |
| Host | smart-60db0870-07b9-41a3-8aa4-056986dde176 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695957292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2695957292 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/26.kmac_app.1894558548 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4000520224 ps |
| CPU time | 242.18 seconds |
| Started | May 26 02:57:06 PM PDT 24 |
| Finished | May 26 03:01:09 PM PDT 24 |
| Peak memory | 242652 kb |
| Host | smart-50375099-2631-4e13-817b-6a159bc1d30d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1894558548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1894558548 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_app/latest |
| Test location | /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.4214793857 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 105651846 ps |
| CPU time | 2.47 seconds |
| Started | May 26 01:55:12 PM PDT 24 |
| Finished | May 26 01:55:15 PM PDT 24 |
| Peak memory | 206768 kb |
| Host | smart-4f91aec1-4cb7-482f-a2e8-54c75ddffd71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214793857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.42147 93857 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/default/2.kmac_test_vectors_shake_256.3699160593 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2452707652920 ps |
| CPU time | 4916.64 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 04:16:57 PM PDT 24 |
| Peak memory | 572308 kb |
| Host | smart-2a1390da-87c4-4085-a075-2e5f9f00b73a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3699160593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3699160593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/34.kmac_entropy_refresh.3022826636 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 5752584982 ps |
| CPU time | 124.04 seconds |
| Started | May 26 02:58:38 PM PDT 24 |
| Finished | May 26 03:00:43 PM PDT 24 |
| Peak memory | 233444 kb |
| Host | smart-bd0c2574-6e96-4685-b43f-3c6e54434c8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022826636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3022826636 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/34.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/1.kmac_app.1842730833 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 9307954382 ps |
| CPU time | 202.98 seconds |
| Started | May 26 02:54:59 PM PDT 24 |
| Finished | May 26 02:58:26 PM PDT 24 |
| Peak memory | 239960 kb |
| Host | smart-d431d085-6a64-47d3-b777-4eefe0ec54cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842730833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1842730833 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_app/latest |
| Test location | /workspace/coverage/default/26.kmac_test_vectors_shake_128.2786668952 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 170459073394 ps |
| CPU time | 4881.08 seconds |
| Started | May 26 02:57:03 PM PDT 24 |
| Finished | May 26 04:18:25 PM PDT 24 |
| Peak memory | 641344 kb |
| Host | smart-98a83375-aa9e-4098-ba70-04c1276eb24d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2786668952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2786668952 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/27.kmac_sideload.1384017483 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 49808055475 ps |
| CPU time | 336.93 seconds |
| Started | May 26 02:57:14 PM PDT 24 |
| Finished | May 26 03:02:51 PM PDT 24 |
| Peak memory | 246796 kb |
| Host | smart-3dc79d10-d92b-47a4-960a-b28923aeb131 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384017483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1384017483 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_sideload/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1718204721 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 571126764 ps |
| CPU time | 8.17 seconds |
| Started | May 26 01:54:58 PM PDT 24 |
| Finished | May 26 01:55:08 PM PDT 24 |
| Peak memory | 214860 kb |
| Host | smart-3221a9fc-9973-46fb-b5f0-95ae6e8f1f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718204721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1718204 721 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1630971234 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 972566005 ps |
| CPU time | 19.13 seconds |
| Started | May 26 01:55:06 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 206736 kb |
| Host | smart-ac12918e-b925-42c0-936a-5802e6ae89f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630971234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1630971 234 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.487272535 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 17742518 ps |
| CPU time | 0.93 seconds |
| Started | May 26 01:55:05 PM PDT 24 |
| Finished | May 26 01:55:06 PM PDT 24 |
| Peak memory | 206516 kb |
| Host | smart-279e189f-82d5-41be-b7cb-a8e58ae8f7fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487272535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.48727253 5 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1757209659 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 130094925 ps |
| CPU time | 2.2 seconds |
| Started | May 26 01:55:01 PM PDT 24 |
| Finished | May 26 01:55:04 PM PDT 24 |
| Peak memory | 215604 kb |
| Host | smart-64c969b8-8cc1-44fb-a0b8-9dfdb67555b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757209659 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.1757209659 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2996232037 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 82817058 ps |
| CPU time | 1.12 seconds |
| Started | May 26 01:55:04 PM PDT 24 |
| Finished | May 26 01:55:06 PM PDT 24 |
| Peak memory | 214908 kb |
| Host | smart-bd4ce2ec-3860-4be1-b476-c153597f53dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996232037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2996232037 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_intr_test.278322277 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 19042702 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:55:05 PM PDT 24 |
| Finished | May 26 01:55:07 PM PDT 24 |
| Peak memory | 206516 kb |
| Host | smart-9f094141-e203-46c0-bec4-8b1d43d3b00d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278322277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.278322277 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1327999796 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 203594462 ps |
| CPU time | 1.27 seconds |
| Started | May 26 01:55:08 PM PDT 24 |
| Finished | May 26 01:55:09 PM PDT 24 |
| Peak memory | 214964 kb |
| Host | smart-b5db653a-8a98-47f0-964d-236ad7218363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327999796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.1327999796 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2057344231 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 23725135 ps |
| CPU time | 0.81 seconds |
| Started | May 26 01:55:06 PM PDT 24 |
| Finished | May 26 01:55:08 PM PDT 24 |
| Peak memory | 206596 kb |
| Host | smart-8625cfaa-44bc-4354-89ac-ce9a0d46f94b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057344231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2057344231 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1839059022 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 94450943 ps |
| CPU time | 1.59 seconds |
| Started | May 26 01:54:57 PM PDT 24 |
| Finished | May 26 01:54:59 PM PDT 24 |
| Peak memory | 215208 kb |
| Host | smart-6c79e7d6-9a83-4500-8690-5ad3c23ac4ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839059022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.1839059022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1122880197 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 91495062 ps |
| CPU time | 0.96 seconds |
| Started | May 26 01:54:57 PM PDT 24 |
| Finished | May 26 01:54:58 PM PDT 24 |
| Peak memory | 206680 kb |
| Host | smart-42505f40-56cd-491d-b413-120ac9f32d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122880197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.1122880197 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1072170915 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 94412069 ps |
| CPU time | 2.24 seconds |
| Started | May 26 01:55:04 PM PDT 24 |
| Finished | May 26 01:55:07 PM PDT 24 |
| Peak memory | 215096 kb |
| Host | smart-0b74bfa6-bec6-4305-bf2a-8ad0c006dc10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072170915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1072170915 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1282161271 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 142231269 ps |
| CPU time | 3.81 seconds |
| Started | May 26 01:55:06 PM PDT 24 |
| Finished | May 26 01:55:10 PM PDT 24 |
| Peak memory | 214928 kb |
| Host | smart-8198b563-06c7-46a3-b45b-58ead53c18f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282161271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.12821 61271 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.1080023097 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 75557449 ps |
| CPU time | 4.49 seconds |
| Started | May 26 01:55:08 PM PDT 24 |
| Finished | May 26 01:55:13 PM PDT 24 |
| Peak memory | 214892 kb |
| Host | smart-a7f6b361-5c60-4cc7-bf56-7787e32895e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080023097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1080023 097 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2751043237 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 3862470642 ps |
| CPU time | 18.86 seconds |
| Started | May 26 01:55:07 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 206784 kb |
| Host | smart-ac9aaffe-89c8-4885-9532-e579b78db18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751043237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2751043 237 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1926760691 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 29873791 ps |
| CPU time | 0.97 seconds |
| Started | May 26 01:55:02 PM PDT 24 |
| Finished | May 26 01:55:03 PM PDT 24 |
| Peak memory | 206536 kb |
| Host | smart-35963cba-ba9a-4123-97a0-ab68b616f6b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926760691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1926760 691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3974819266 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 100214902 ps |
| CPU time | 2.21 seconds |
| Started | May 26 01:55:08 PM PDT 24 |
| Finished | May 26 01:55:11 PM PDT 24 |
| Peak memory | 216108 kb |
| Host | smart-b465d024-33e5-47a3-8df2-46a4f8e8cae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974819266 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.3974819266 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1601805675 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 126727010 ps |
| CPU time | 1.16 seconds |
| Started | May 26 01:54:59 PM PDT 24 |
| Finished | May 26 01:55:01 PM PDT 24 |
| Peak memory | 214952 kb |
| Host | smart-d1979e9a-4a74-4f1e-ad84-37234d9c6239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601805675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1601805675 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_intr_test.3322034735 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 15082455 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:05 PM PDT 24 |
| Finished | May 26 01:55:07 PM PDT 24 |
| Peak memory | 206500 kb |
| Host | smart-f6a2092d-8fce-48be-b7eb-ccebfc56dddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322034735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3322034735 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2107728042 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 71493698 ps |
| CPU time | 1.41 seconds |
| Started | May 26 01:54:59 PM PDT 24 |
| Finished | May 26 01:55:02 PM PDT 24 |
| Peak memory | 214904 kb |
| Host | smart-1a0fd1d2-ae59-423c-b695-585e69feddd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107728042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.2107728042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_mem_walk.1970071728 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 17712432 ps |
| CPU time | 0.71 seconds |
| Started | May 26 01:54:58 PM PDT 24 |
| Finished | May 26 01:55:00 PM PDT 24 |
| Peak memory | 206580 kb |
| Host | smart-c9c94c9f-3f07-4c19-b808-518065dac89a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970071728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1970071728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.692760209 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 141287051 ps |
| CPU time | 2.17 seconds |
| Started | May 26 01:55:09 PM PDT 24 |
| Finished | May 26 01:55:12 PM PDT 24 |
| Peak memory | 215200 kb |
| Host | smart-e94ae1a3-9387-455a-a3bd-d7053bb96ed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692760209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_ outstanding.692760209 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1562869378 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 39852151 ps |
| CPU time | 1.34 seconds |
| Started | May 26 01:54:59 PM PDT 24 |
| Finished | May 26 01:55:01 PM PDT 24 |
| Peak memory | 215492 kb |
| Host | smart-d4b7a638-1ca6-4e62-8c68-3a641d54b4c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562869378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.1562869378 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3812668776 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 57204497 ps |
| CPU time | 1.93 seconds |
| Started | May 26 01:54:58 PM PDT 24 |
| Finished | May 26 01:55:01 PM PDT 24 |
| Peak memory | 223244 kb |
| Host | smart-bda8bce1-3201-41e4-a056-2ca400ce8f5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812668776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3812668776 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.283664534 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 802261908 ps |
| CPU time | 4.7 seconds |
| Started | May 26 01:55:05 PM PDT 24 |
| Finished | May 26 01:55:11 PM PDT 24 |
| Peak memory | 206688 kb |
| Host | smart-ae65e61d-1a4e-4dad-ac8d-c51ec5f4059a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283664534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.283664 534 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1446185927 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 35225096 ps |
| CPU time | 2.36 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 216192 kb |
| Host | smart-f63f19ca-b9b7-4311-b259-de12ea82f645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446185927 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1446185927 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2778081040 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 56522276 ps |
| CPU time | 1 seconds |
| Started | May 26 01:55:24 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-e45db449-1a4b-4e30-a8e4-35d8771b526b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778081040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2778081040 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.kmac_intr_test.2928083452 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 14322844 ps |
| CPU time | 0.76 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:23 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-81eb440b-df88-491d-9471-4f3152895e35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928083452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2928083452 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1542641095 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 42387667 ps |
| CPU time | 1.4 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:24 PM PDT 24 |
| Peak memory | 215132 kb |
| Host | smart-34465627-4ffc-45f1-a0bf-bf15e56a5d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542641095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.1542641095 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2930190344 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 58210891 ps |
| CPU time | 1 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 215308 kb |
| Host | smart-8d90d4d8-e1c5-4d8f-8a64-12c69f54eef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930190344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.2930190344 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1744313721 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 199941722 ps |
| CPU time | 1.7 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 215052 kb |
| Host | smart-d227883a-bb39-4e06-93c3-435d3ccdef75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744313721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1744313721 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2896036868 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 435972968 ps |
| CPU time | 2.81 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 215128 kb |
| Host | smart-2b01fcb8-7387-4b44-8433-3d4c29fb358b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896036868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2896 036868 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.602490446 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 38153351 ps |
| CPU time | 2.36 seconds |
| Started | May 26 01:55:32 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 217572 kb |
| Host | smart-78884c89-9480-4da0-a97f-910cc34dfc64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602490446 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.602490446 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2459675836 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 232012952 ps |
| CPU time | 1.06 seconds |
| Started | May 26 01:55:31 PM PDT 24 |
| Finished | May 26 01:55:32 PM PDT 24 |
| Peak memory | 206452 kb |
| Host | smart-2d7a2d8e-88d7-41d3-9f3c-694e21d29b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459675836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2459675836 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.kmac_intr_test.1244091799 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 14668531 ps |
| CPU time | 0.81 seconds |
| Started | May 26 01:55:31 PM PDT 24 |
| Finished | May 26 01:55:32 PM PDT 24 |
| Peak memory | 206468 kb |
| Host | smart-0d0bdc2f-58eb-4792-a534-bc691e022e19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244091799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1244091799 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.512354499 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 220958566 ps |
| CPU time | 2.58 seconds |
| Started | May 26 01:55:32 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 214852 kb |
| Host | smart-3f2b3fe2-fbaa-4a45-87fd-53cc6f7ae05b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512354499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr _outstanding.512354499 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.kmac_tl_errors.4041195260 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 133873661 ps |
| CPU time | 3.22 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 215148 kb |
| Host | smart-ff0b1f80-5fe7-41f4-9b28-636ca8f88452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041195260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.4041195260 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.657855213 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 455084976 ps |
| CPU time | 3.13 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:27 PM PDT 24 |
| Peak memory | 215024 kb |
| Host | smart-568c294b-7237-4c51-86ca-2a0225b87895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657855213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.65785 5213 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2320912728 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 95882634 ps |
| CPU time | 1.71 seconds |
| Started | May 26 01:55:33 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 215112 kb |
| Host | smart-4d93766f-d837-4864-8d5b-abec6376350c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320912728 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2320912728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2021325702 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 31544329 ps |
| CPU time | 0.98 seconds |
| Started | May 26 01:55:29 PM PDT 24 |
| Finished | May 26 01:55:30 PM PDT 24 |
| Peak memory | 206720 kb |
| Host | smart-aa88d553-8771-4d82-b317-b4cd39f9d7bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021325702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2021325702 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.kmac_intr_test.749306438 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 23529402 ps |
| CPU time | 0.82 seconds |
| Started | May 26 01:55:33 PM PDT 24 |
| Finished | May 26 01:55:34 PM PDT 24 |
| Peak memory | 206548 kb |
| Host | smart-a3262bc0-43bd-4592-bf63-6b45bee68124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749306438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.749306438 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.44163023 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 432627479 ps |
| CPU time | 2.2 seconds |
| Started | May 26 01:55:30 PM PDT 24 |
| Finished | May 26 01:55:32 PM PDT 24 |
| Peak memory | 215228 kb |
| Host | smart-1ff2e4fa-c0a2-466d-bfef-9c4780ab155d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44163023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_ outstanding.44163023 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2379831805 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 50013224 ps |
| CPU time | 1.01 seconds |
| Started | May 26 01:55:34 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 206904 kb |
| Host | smart-97d345fb-1033-48e7-94d3-ddfebbc92aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379831805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.2379831805 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.kmac_tl_errors.45608222 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 43503345 ps |
| CPU time | 2.71 seconds |
| Started | May 26 01:55:32 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 223220 kb |
| Host | smart-992dc257-bd93-4c34-8771-35681ff7622b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45608222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.45608222 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1307576364 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 359533828 ps |
| CPU time | 2.95 seconds |
| Started | May 26 01:55:32 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 206760 kb |
| Host | smart-946cabe4-d0ee-467e-a3ba-f94c350aa7a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307576364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1307 576364 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1132618559 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 78826878 ps |
| CPU time | 1.54 seconds |
| Started | May 26 01:55:32 PM PDT 24 |
| Finished | May 26 01:55:34 PM PDT 24 |
| Peak memory | 214948 kb |
| Host | smart-d53be2e6-d8cc-4375-b3b0-452f7b74a4cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132618559 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.1132618559 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1796335911 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 41902619 ps |
| CPU time | 0.93 seconds |
| Started | May 26 01:55:30 PM PDT 24 |
| Finished | May 26 01:55:32 PM PDT 24 |
| Peak memory | 206552 kb |
| Host | smart-e54e1768-d848-4687-a57d-226187c18bcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796335911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1796335911 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.kmac_intr_test.1934965793 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 14185107 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:30 PM PDT 24 |
| Finished | May 26 01:55:32 PM PDT 24 |
| Peak memory | 206472 kb |
| Host | smart-cf50dfc4-775b-465a-91d7-d3e0f9b74978 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934965793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1934965793 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1405432587 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 96102400 ps |
| CPU time | 2.55 seconds |
| Started | May 26 01:55:29 PM PDT 24 |
| Finished | May 26 01:55:32 PM PDT 24 |
| Peak memory | 215336 kb |
| Host | smart-78729dda-88d7-4882-ae89-2063fe76fc9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405432587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.1405432587 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2555300371 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 81473541 ps |
| CPU time | 1.44 seconds |
| Started | May 26 01:55:31 PM PDT 24 |
| Finished | May 26 01:55:34 PM PDT 24 |
| Peak memory | 215460 kb |
| Host | smart-5f380e55-da72-4690-a444-90d7004b2a55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555300371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.2555300371 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.481942389 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 361383054 ps |
| CPU time | 2.24 seconds |
| Started | May 26 01:55:34 PM PDT 24 |
| Finished | May 26 01:55:37 PM PDT 24 |
| Peak memory | 215524 kb |
| Host | smart-edbee8e0-66e1-43c0-a98a-0f44d1c1b3d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481942389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac _shadow_reg_errors_with_csr_rw.481942389 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.kmac_tl_errors.825132998 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 257347016 ps |
| CPU time | 1.83 seconds |
| Started | May 26 01:55:33 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 215084 kb |
| Host | smart-0adaa7db-b0b8-46ef-88b6-79f955eec63f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825132998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.825132998 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2956324135 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 74273347 ps |
| CPU time | 2.32 seconds |
| Started | May 26 01:55:34 PM PDT 24 |
| Finished | May 26 01:55:38 PM PDT 24 |
| Peak memory | 216164 kb |
| Host | smart-7a53b4eb-93b1-43b6-a58e-fb26d535b24a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956324135 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2956324135 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.kmac_csr_rw.1740683099 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 31151270 ps |
| CPU time | 1.18 seconds |
| Started | May 26 01:55:33 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 206756 kb |
| Host | smart-10ebe191-709a-4416-a71d-380b68dec66e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740683099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1740683099 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.kmac_intr_test.783522442 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 75051400 ps |
| CPU time | 0.74 seconds |
| Started | May 26 01:55:32 PM PDT 24 |
| Finished | May 26 01:55:33 PM PDT 24 |
| Peak memory | 206492 kb |
| Host | smart-81e97e65-c7ab-485c-a3da-a4586d950d58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783522442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.783522442 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1860042712 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 70481195 ps |
| CPU time | 1.8 seconds |
| Started | May 26 01:55:33 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 215260 kb |
| Host | smart-bf09432d-b492-4bdd-9748-5d3d5a96c064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860042712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.1860042712 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2777732572 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 58504453 ps |
| CPU time | 1.61 seconds |
| Started | May 26 01:55:34 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-03a84924-d640-4406-8d7d-661a02d007b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777732572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.2777732572 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2690282356 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 90042176 ps |
| CPU time | 1.44 seconds |
| Started | May 26 01:55:31 PM PDT 24 |
| Finished | May 26 01:55:33 PM PDT 24 |
| Peak memory | 215032 kb |
| Host | smart-0a2d2364-ead6-4a4e-bb9b-a10af00f165d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690282356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2690282356 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3393997506 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 372922178 ps |
| CPU time | 2.99 seconds |
| Started | May 26 01:55:29 PM PDT 24 |
| Finished | May 26 01:55:33 PM PDT 24 |
| Peak memory | 214968 kb |
| Host | smart-456b45c0-82e5-4b03-b8e2-ffce64587232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393997506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3393 997506 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3389563734 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 960105464 ps |
| CPU time | 2.54 seconds |
| Started | May 26 01:55:38 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 223076 kb |
| Host | smart-a1e8b71e-dbf4-4e9e-a17d-683a63b8f1d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389563734 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.3389563734 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2878762902 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 38971024 ps |
| CPU time | 0.94 seconds |
| Started | May 26 01:55:41 PM PDT 24 |
| Finished | May 26 01:55:43 PM PDT 24 |
| Peak memory | 206552 kb |
| Host | smart-336ae6c4-3b6f-4d9f-b91c-75c1563745ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878762902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2878762902 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.kmac_intr_test.3834930948 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 12570118 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:55:32 PM PDT 24 |
| Finished | May 26 01:55:33 PM PDT 24 |
| Peak memory | 206476 kb |
| Host | smart-9e6aa60a-13c9-41bf-b951-111edf9d51e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834930948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3834930948 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.127727483 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 93781721 ps |
| CPU time | 2.47 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:42 PM PDT 24 |
| Peak memory | 215244 kb |
| Host | smart-39b91597-30bd-426b-ba8f-13d26d7b4273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127727483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr _outstanding.127727483 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2916148114 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 22381408 ps |
| CPU time | 0.94 seconds |
| Started | May 26 01:55:32 PM PDT 24 |
| Finished | May 26 01:55:33 PM PDT 24 |
| Peak memory | 215272 kb |
| Host | smart-28ce69f7-8919-45ea-956b-7096058da91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916148114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.2916148114 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.198439827 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 163628993 ps |
| CPU time | 1.76 seconds |
| Started | May 26 01:55:33 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 215484 kb |
| Host | smart-ff83695c-ab39-4fa4-8a02-395324866802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198439827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac _shadow_reg_errors_with_csr_rw.198439827 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.kmac_tl_errors.995314677 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 1567615796 ps |
| CPU time | 2.66 seconds |
| Started | May 26 01:55:33 PM PDT 24 |
| Finished | May 26 01:55:36 PM PDT 24 |
| Peak memory | 218896 kb |
| Host | smart-e7d6bb22-1618-467d-a768-fbf70fc749f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995314677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.995314677 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1050490296 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 733688914 ps |
| CPU time | 4.8 seconds |
| Started | May 26 01:55:30 PM PDT 24 |
| Finished | May 26 01:55:35 PM PDT 24 |
| Peak memory | 206768 kb |
| Host | smart-572d1759-abc8-4a7c-9684-04b90e3ceec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050490296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1050 490296 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.161409840 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 21444680 ps |
| CPU time | 1.45 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 215004 kb |
| Host | smart-6c39b390-129a-4241-89fe-6b9c5489a56c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161409840 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.161409840 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2991045930 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 47048447 ps |
| CPU time | 1.11 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 206732 kb |
| Host | smart-30009cb6-1a9c-472d-aab0-7ada88a7e4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991045930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2991045930 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.kmac_intr_test.2824173226 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 27587697 ps |
| CPU time | 0.71 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 206568 kb |
| Host | smart-3a1ce60a-09fa-4f84-a0c3-ba955ef614ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824173226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2824173226 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3641774269 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 196177158 ps |
| CPU time | 1.59 seconds |
| Started | May 26 01:55:37 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 215312 kb |
| Host | smart-e6ed2174-c5ed-4625-85a7-803ef90dc024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641774269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.3641774269 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.159080284 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 99359867 ps |
| CPU time | 1.13 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 215512 kb |
| Host | smart-45a22dfd-cb5c-47b6-b92a-0ec1f26153a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159080284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_ errors.159080284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.194897430 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 139431183 ps |
| CPU time | 1.97 seconds |
| Started | May 26 01:55:42 PM PDT 24 |
| Finished | May 26 01:55:44 PM PDT 24 |
| Peak memory | 215464 kb |
| Host | smart-09111b63-523a-4f18-9b9f-a3707687491a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194897430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac _shadow_reg_errors_with_csr_rw.194897430 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3739065900 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 142032444 ps |
| CPU time | 2.2 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:42 PM PDT 24 |
| Peak memory | 215088 kb |
| Host | smart-617f1700-23ee-4762-a60d-f66f1070ed27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739065900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3739065900 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.858397297 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 423817857 ps |
| CPU time | 2.73 seconds |
| Started | May 26 01:55:38 PM PDT 24 |
| Finished | May 26 01:55:42 PM PDT 24 |
| Peak memory | 206704 kb |
| Host | smart-c0f38ac3-cbdd-4ff0-98e9-5cdb2baaef05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858397297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.85839 7297 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.660300841 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 24340022 ps |
| CPU time | 1.45 seconds |
| Started | May 26 01:55:36 PM PDT 24 |
| Finished | May 26 01:55:38 PM PDT 24 |
| Peak memory | 223108 kb |
| Host | smart-aa2bbce7-462a-4b9b-8ef3-c890899b4954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660300841 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.660300841 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1263292362 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 56138855 ps |
| CPU time | 1.04 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 206724 kb |
| Host | smart-38300238-bfb7-4fc0-b0bc-a4d8e842fa7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263292362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1263292362 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.kmac_intr_test.3121951575 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 18339851 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:55:37 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 206516 kb |
| Host | smart-f0bb023a-93c4-4841-a676-d8d201858f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121951575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3121951575 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2801456927 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 91051607 ps |
| CPU time | 2.53 seconds |
| Started | May 26 01:55:41 PM PDT 24 |
| Finished | May 26 01:55:44 PM PDT 24 |
| Peak memory | 215424 kb |
| Host | smart-e9e00fcc-b7df-4609-a4d1-4ac3866e1230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801456927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.2801456927 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.393811860 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 16652471 ps |
| CPU time | 0.83 seconds |
| Started | May 26 01:55:38 PM PDT 24 |
| Finished | May 26 01:55:40 PM PDT 24 |
| Peak memory | 206592 kb |
| Host | smart-9656a612-6b6b-4026-93c2-861a469ba9f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393811860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_ errors.393811860 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1363164404 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 151287349 ps |
| CPU time | 2.83 seconds |
| Started | May 26 01:55:37 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 215008 kb |
| Host | smart-8c475282-2247-4c7b-952d-40a071e87092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363164404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1363164404 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.83863225 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 37931085 ps |
| CPU time | 2.33 seconds |
| Started | May 26 01:55:38 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 216704 kb |
| Host | smart-e38164a6-5ab5-462d-a64c-1abca4fe3376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83863225 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.83863225 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1279778060 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 28626541 ps |
| CPU time | 1.14 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 206844 kb |
| Host | smart-bf8c6a6a-88e4-4c3f-baff-487500bb17ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279778060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1279778060 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.kmac_intr_test.3274915003 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 25869259 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:40 PM PDT 24 |
| Peak memory | 206560 kb |
| Host | smart-2ecf5039-43c6-4fef-8a73-4eb14c6a0142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274915003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3274915003 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3506139798 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 69056665 ps |
| CPU time | 2.25 seconds |
| Started | May 26 01:55:40 PM PDT 24 |
| Finished | May 26 01:55:43 PM PDT 24 |
| Peak memory | 214952 kb |
| Host | smart-5540f182-a499-4462-bf53-3270658c6d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506139798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.3506139798 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2127220210 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 136065048 ps |
| CPU time | 1.3 seconds |
| Started | May 26 01:55:36 PM PDT 24 |
| Finished | May 26 01:55:38 PM PDT 24 |
| Peak memory | 215496 kb |
| Host | smart-562189ea-40fb-45eb-8264-6f37e7d6c8d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127220210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.2127220210 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2219716022 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 176525304 ps |
| CPU time | 1.69 seconds |
| Started | May 26 01:55:37 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 215436 kb |
| Host | smart-46bd9792-ec64-4217-b801-4f8fd7659a74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219716022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.2219716022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2029416892 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 84899991 ps |
| CPU time | 2.67 seconds |
| Started | May 26 01:55:36 PM PDT 24 |
| Finished | May 26 01:55:40 PM PDT 24 |
| Peak memory | 215040 kb |
| Host | smart-8c491c99-aa4c-40c1-af71-b4bcbe735e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029416892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2029416892 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.1545040916 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 365090149 ps |
| CPU time | 2.71 seconds |
| Started | May 26 01:55:42 PM PDT 24 |
| Finished | May 26 01:55:45 PM PDT 24 |
| Peak memory | 206744 kb |
| Host | smart-b9681064-4200-4e3d-b29a-08d9eafb5e50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545040916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1545 040916 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3714320832 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 491245291 ps |
| CPU time | 2.53 seconds |
| Started | May 26 01:55:36 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 216988 kb |
| Host | smart-cd2a952b-e600-4bc9-8797-a0612ce2a341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714320832 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3714320832 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1727619395 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 20385431 ps |
| CPU time | 0.9 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:40 PM PDT 24 |
| Peak memory | 206560 kb |
| Host | smart-0f72c60c-3067-40c3-9790-78ef330da5bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727619395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1727619395 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1605936653 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 51305038 ps |
| CPU time | 1.64 seconds |
| Started | May 26 01:55:40 PM PDT 24 |
| Finished | May 26 01:55:43 PM PDT 24 |
| Peak memory | 214800 kb |
| Host | smart-d2366e20-0767-448e-8e7a-b714065d9f2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605936653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.1605936653 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3490960642 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 33812347 ps |
| CPU time | 0.95 seconds |
| Started | May 26 01:55:37 PM PDT 24 |
| Finished | May 26 01:55:39 PM PDT 24 |
| Peak memory | 206704 kb |
| Host | smart-eb4bc641-88bb-4938-9315-4e969a6ccaa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490960642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.3490960642 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2117922284 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 829725013 ps |
| CPU time | 2.59 seconds |
| Started | May 26 01:55:37 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 223532 kb |
| Host | smart-88a6966c-883a-4a30-84fe-9faf89ec02ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117922284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.2117922284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3377265241 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 115007065 ps |
| CPU time | 2.96 seconds |
| Started | May 26 01:55:38 PM PDT 24 |
| Finished | May 26 01:55:42 PM PDT 24 |
| Peak memory | 215072 kb |
| Host | smart-be38c598-b622-4ea9-b73f-8722bb93c5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377265241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3377265241 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.39559027 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 171960197 ps |
| CPU time | 3.85 seconds |
| Started | May 26 01:55:40 PM PDT 24 |
| Finished | May 26 01:55:45 PM PDT 24 |
| Peak memory | 214804 kb |
| Host | smart-7d9df503-477d-46a4-aa21-b63944a998fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39559027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.395590 27 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2483111333 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 408539878 ps |
| CPU time | 4.81 seconds |
| Started | May 26 01:55:05 PM PDT 24 |
| Finished | May 26 01:55:10 PM PDT 24 |
| Peak memory | 206848 kb |
| Host | smart-6e227e56-5181-40a7-9e23-4396ca108373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483111333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2483111 333 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2019713453 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 157921241 ps |
| CPU time | 8.43 seconds |
| Started | May 26 01:55:06 PM PDT 24 |
| Finished | May 26 01:55:16 PM PDT 24 |
| Peak memory | 206756 kb |
| Host | smart-70177467-aff6-492a-8b85-0a7284d82e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019713453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2019713 453 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.23369149 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 36814498 ps |
| CPU time | 0.98 seconds |
| Started | May 26 01:55:08 PM PDT 24 |
| Finished | May 26 01:55:10 PM PDT 24 |
| Peak memory | 206540 kb |
| Host | smart-1537a297-b9a9-443e-a6ee-cce97c0a93a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23369149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.23369149 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1199323570 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 242512290 ps |
| CPU time | 1.6 seconds |
| Started | May 26 01:55:08 PM PDT 24 |
| Finished | May 26 01:55:11 PM PDT 24 |
| Peak memory | 222172 kb |
| Host | smart-adaab501-253b-4290-b7f9-dc19b5ab8da1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199323570 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.1199323570 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_csr_rw.3068796014 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 95307463 ps |
| CPU time | 1.13 seconds |
| Started | May 26 01:55:06 PM PDT 24 |
| Finished | May 26 01:55:08 PM PDT 24 |
| Peak memory | 206792 kb |
| Host | smart-fc7a6520-349c-4e60-a196-41ec88e564a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068796014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3068796014 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_intr_test.437307756 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 15931894 ps |
| CPU time | 0.76 seconds |
| Started | May 26 01:55:05 PM PDT 24 |
| Finished | May 26 01:55:07 PM PDT 24 |
| Peak memory | 206532 kb |
| Host | smart-bbe6c41c-557e-40c0-9e20-85feebe97826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437307756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.437307756 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1521677427 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 14036219 ps |
| CPU time | 0.73 seconds |
| Started | May 26 01:55:08 PM PDT 24 |
| Finished | May 26 01:55:09 PM PDT 24 |
| Peak memory | 206528 kb |
| Host | smart-cdfd5f09-2615-45e6-9ba3-b368cce5b136 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521677427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1521677427 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2651558463 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 163642903 ps |
| CPU time | 1.43 seconds |
| Started | May 26 01:55:05 PM PDT 24 |
| Finished | May 26 01:55:07 PM PDT 24 |
| Peak memory | 215188 kb |
| Host | smart-1cf7f018-b00d-4a2a-9fde-9660c5580a34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651558463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.2651558463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4004079571 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 88276630 ps |
| CPU time | 2.41 seconds |
| Started | May 26 01:55:05 PM PDT 24 |
| Finished | May 26 01:55:08 PM PDT 24 |
| Peak memory | 223600 kb |
| Host | smart-b9444746-cafd-49da-98d4-f8205c1651c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004079571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.4004079571 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2062086361 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 165308012 ps |
| CPU time | 1.48 seconds |
| Started | May 26 01:55:12 PM PDT 24 |
| Finished | May 26 01:55:14 PM PDT 24 |
| Peak memory | 217056 kb |
| Host | smart-55ce73d1-bc94-4282-a0fd-5d4927d59208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062086361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2062086361 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3611667905 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 54604845 ps |
| CPU time | 2.37 seconds |
| Started | May 26 01:55:08 PM PDT 24 |
| Finished | May 26 01:55:11 PM PDT 24 |
| Peak memory | 214896 kb |
| Host | smart-e3387132-1822-4afc-8238-2a2c1aa4c3aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611667905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.36116 67905 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.kmac_intr_test.838151697 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 17147148 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:55:36 PM PDT 24 |
| Finished | May 26 01:55:37 PM PDT 24 |
| Peak memory | 206496 kb |
| Host | smart-d29b5555-23dc-4483-97a5-ed9b120732e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838151697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.838151697 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.kmac_intr_test.1063312170 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 16451969 ps |
| CPU time | 0.82 seconds |
| Started | May 26 01:55:40 PM PDT 24 |
| Finished | May 26 01:55:41 PM PDT 24 |
| Peak memory | 206400 kb |
| Host | smart-eaaeb0c9-a453-4a35-b600-4d3d78fa89fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063312170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1063312170 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.kmac_intr_test.2043584107 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 116422249 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:55:39 PM PDT 24 |
| Finished | May 26 01:55:40 PM PDT 24 |
| Peak memory | 206548 kb |
| Host | smart-1967260b-aee8-4cc3-8397-6300365094ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043584107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2043584107 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.kmac_intr_test.497013926 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 47117800 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:41 PM PDT 24 |
| Finished | May 26 01:55:42 PM PDT 24 |
| Peak memory | 206544 kb |
| Host | smart-b38349ee-fc9e-44cd-bc9b-6bb3ca7bd517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497013926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.497013926 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.kmac_intr_test.3591892110 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 28642383 ps |
| CPU time | 0.82 seconds |
| Started | May 26 01:55:49 PM PDT 24 |
| Finished | May 26 01:55:50 PM PDT 24 |
| Peak memory | 206544 kb |
| Host | smart-37cbc11e-e4df-439b-b379-ab64bb1a1005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591892110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3591892110 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.kmac_intr_test.4077259675 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 16530705 ps |
| CPU time | 0.81 seconds |
| Started | May 26 01:55:46 PM PDT 24 |
| Finished | May 26 01:55:48 PM PDT 24 |
| Peak memory | 206544 kb |
| Host | smart-4a9d0c08-2d6d-4b7b-b9a7-0fd7cebbe90d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077259675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.4077259675 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.kmac_intr_test.1785451204 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 23443638 ps |
| CPU time | 0.79 seconds |
| Started | May 26 01:55:47 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 206688 kb |
| Host | smart-798a52e6-2da7-4e51-92b3-594318b38dd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785451204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1785451204 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.kmac_intr_test.947432129 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 11235257 ps |
| CPU time | 0.76 seconds |
| Started | May 26 01:55:46 PM PDT 24 |
| Finished | May 26 01:55:48 PM PDT 24 |
| Peak memory | 206532 kb |
| Host | smart-58026283-6572-4846-9daf-88f3699e9f50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947432129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.947432129 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.kmac_intr_test.1536818000 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 12765659 ps |
| CPU time | 0.73 seconds |
| Started | May 26 01:55:50 PM PDT 24 |
| Finished | May 26 01:55:51 PM PDT 24 |
| Peak memory | 206568 kb |
| Host | smart-af19e67c-f8d1-4762-9cf8-37803bfe6756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536818000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1536818000 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.kmac_intr_test.2262181884 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 143549355 ps |
| CPU time | 0.76 seconds |
| Started | May 26 01:55:45 PM PDT 24 |
| Finished | May 26 01:55:46 PM PDT 24 |
| Peak memory | 206548 kb |
| Host | smart-09c33f1f-7d01-42d6-a8b0-0907012e8aae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262181884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2262181884 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1948961022 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 536400392 ps |
| CPU time | 8.07 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:24 PM PDT 24 |
| Peak memory | 206764 kb |
| Host | smart-cccf2c9c-1730-49d5-a107-0979032b3ee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948961022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1948961 022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3713303862 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 626642876 ps |
| CPU time | 8.3 seconds |
| Started | May 26 01:55:17 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 206668 kb |
| Host | smart-7dbe9559-f663-430c-8353-b9ad92afc0d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713303862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3713303 862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3563084359 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 20089034 ps |
| CPU time | 0.97 seconds |
| Started | May 26 01:55:17 PM PDT 24 |
| Finished | May 26 01:55:18 PM PDT 24 |
| Peak memory | 206464 kb |
| Host | smart-ba1c2d10-6ece-4d2b-b0e5-30fda308c569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563084359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3563084 359 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.1317970186 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 27876792 ps |
| CPU time | 1.8 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:18 PM PDT 24 |
| Peak memory | 215628 kb |
| Host | smart-c8977e22-3aa1-4187-9f61-0b9b6b3fc277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317970186 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.1317970186 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_csr_rw.4104980377 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 22475640 ps |
| CPU time | 0.94 seconds |
| Started | May 26 01:55:17 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 206520 kb |
| Host | smart-df74a664-377d-4048-bf27-8281dead3210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104980377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4104980377 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_intr_test.3491235863 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 12299743 ps |
| CPU time | 0.74 seconds |
| Started | May 26 01:55:16 PM PDT 24 |
| Finished | May 26 01:55:18 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-3b4a265a-8aff-4db6-9be2-4afda64f72c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491235863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3491235863 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.3165301911 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 123808094 ps |
| CPU time | 1.54 seconds |
| Started | May 26 01:55:06 PM PDT 24 |
| Finished | May 26 01:55:08 PM PDT 24 |
| Peak memory | 215152 kb |
| Host | smart-2a8a219b-bd4b-4e07-8cad-f84d6d07d307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165301911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.3165301911 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1890876784 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 119895481 ps |
| CPU time | 0.72 seconds |
| Started | May 26 01:55:11 PM PDT 24 |
| Finished | May 26 01:55:12 PM PDT 24 |
| Peak memory | 206608 kb |
| Host | smart-cf055492-e5be-4c52-9b4b-a84f6f3a6f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890876784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1890876784 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3295767491 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 59304005 ps |
| CPU time | 2.11 seconds |
| Started | May 26 01:55:12 PM PDT 24 |
| Finished | May 26 01:55:15 PM PDT 24 |
| Peak memory | 215384 kb |
| Host | smart-88d71be8-004c-4176-ab29-c07010478eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295767491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.3295767491 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2440917668 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 120809618 ps |
| CPU time | 2.89 seconds |
| Started | May 26 01:55:07 PM PDT 24 |
| Finished | May 26 01:55:10 PM PDT 24 |
| Peak memory | 215520 kb |
| Host | smart-dfe21bb3-7136-4756-b9a5-616140960f91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440917668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.2440917668 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_tl_errors.3482515797 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 473602934 ps |
| CPU time | 2.99 seconds |
| Started | May 26 01:55:08 PM PDT 24 |
| Finished | May 26 01:55:12 PM PDT 24 |
| Peak memory | 215092 kb |
| Host | smart-02571588-9527-4c30-aa7f-50d8163f542f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482515797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3482515797 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.2550997107 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 759667385 ps |
| CPU time | 4.58 seconds |
| Started | May 26 01:55:10 PM PDT 24 |
| Finished | May 26 01:55:14 PM PDT 24 |
| Peak memory | 214888 kb |
| Host | smart-4be0b939-b549-4b11-9095-1db20b77e076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550997107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.25509 97107 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.kmac_intr_test.2033801654 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 38160679 ps |
| CPU time | 0.8 seconds |
| Started | May 26 01:55:45 PM PDT 24 |
| Finished | May 26 01:55:46 PM PDT 24 |
| Peak memory | 206556 kb |
| Host | smart-111313ab-4fab-470e-b418-2575109ffeb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033801654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2033801654 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.kmac_intr_test.4227664347 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 50935954 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:51 PM PDT 24 |
| Finished | May 26 01:55:52 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-12c90fca-acc3-4c4c-9ed1-f9353349a683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227664347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.4227664347 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.kmac_intr_test.2064360467 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 18919835 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:47 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 206560 kb |
| Host | smart-eb00ebc0-c59b-4ceb-bf0b-ce0428cf2790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064360467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2064360467 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.kmac_intr_test.2808206549 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 18803073 ps |
| CPU time | 0.85 seconds |
| Started | May 26 01:55:48 PM PDT 24 |
| Finished | May 26 01:55:50 PM PDT 24 |
| Peak memory | 206500 kb |
| Host | smart-80408277-c518-4da0-8561-aeaa81c0ad3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808206549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2808206549 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.kmac_intr_test.3867247847 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 15726758 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:44 PM PDT 24 |
| Finished | May 26 01:55:45 PM PDT 24 |
| Peak memory | 206568 kb |
| Host | smart-e7169c5d-0e8d-405d-9965-6443bf1abbfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867247847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3867247847 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.kmac_intr_test.1734497985 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 52394411 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:45 PM PDT 24 |
| Finished | May 26 01:55:47 PM PDT 24 |
| Peak memory | 206516 kb |
| Host | smart-bb4eb5f9-92c5-4f29-a5db-55d7b412a77b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734497985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1734497985 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.kmac_intr_test.1117086673 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 71267481 ps |
| CPU time | 0.81 seconds |
| Started | May 26 01:55:46 PM PDT 24 |
| Finished | May 26 01:55:48 PM PDT 24 |
| Peak memory | 206524 kb |
| Host | smart-bedf99db-d1f9-4120-bdde-268e131361a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117086673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1117086673 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.kmac_intr_test.3113768974 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 13837110 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:47 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 206532 kb |
| Host | smart-3a3a065e-b03f-42ad-883a-2cb50cdb7b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113768974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3113768974 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.kmac_intr_test.2248836633 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 31166688 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:46 PM PDT 24 |
| Finished | May 26 01:55:48 PM PDT 24 |
| Peak memory | 206548 kb |
| Host | smart-5f7b5a5e-2723-42f4-8c8f-37b59f5a4d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248836633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2248836633 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.kmac_intr_test.1885290933 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 15548324 ps |
| CPU time | 0.81 seconds |
| Started | May 26 01:55:49 PM PDT 24 |
| Finished | May 26 01:55:50 PM PDT 24 |
| Peak memory | 206472 kb |
| Host | smart-d69f4066-8efb-476e-bc3b-b7b9205e9851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885290933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1885290933 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3232808816 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 537791898 ps |
| CPU time | 5.19 seconds |
| Started | May 26 01:55:20 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 206864 kb |
| Host | smart-86f0ccdf-7c71-4025-8ce0-f904dc8f4164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232808816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3232808 816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3204679278 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 154701081 ps |
| CPU time | 8.38 seconds |
| Started | May 26 01:55:16 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 206760 kb |
| Host | smart-b01a9711-8ef5-4a90-a756-7a3ee3cbcda1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204679278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3204679 278 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.2523283043 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 21001514 ps |
| CPU time | 1.05 seconds |
| Started | May 26 01:55:14 PM PDT 24 |
| Finished | May 26 01:55:15 PM PDT 24 |
| Peak memory | 206760 kb |
| Host | smart-5e682de8-52fb-45c4-b3bc-21bc593dabef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523283043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2523283 043 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3223174120 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 244305686 ps |
| CPU time | 2.36 seconds |
| Started | May 26 01:55:12 PM PDT 24 |
| Finished | May 26 01:55:15 PM PDT 24 |
| Peak memory | 216164 kb |
| Host | smart-5499bea1-a04f-40cd-95b9-4f9089d42e2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223174120 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3223174120 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_csr_rw.199073430 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 51658061 ps |
| CPU time | 0.92 seconds |
| Started | May 26 01:55:13 PM PDT 24 |
| Finished | May 26 01:55:15 PM PDT 24 |
| Peak memory | 206568 kb |
| Host | smart-445b5dea-eed6-47f1-870a-fe54560aa8d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199073430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.199073430 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_intr_test.1400334465 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 36369214 ps |
| CPU time | 0.77 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:16 PM PDT 24 |
| Peak memory | 206544 kb |
| Host | smart-3079cfd2-6d9a-4f28-8e07-c375b9640ca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400334465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1400334465 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.965635247 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 31478188 ps |
| CPU time | 1.2 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:16 PM PDT 24 |
| Peak memory | 214840 kb |
| Host | smart-0697d35e-ea08-48de-a6f1-a3fd344778bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965635247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial _access.965635247 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1945619981 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 16787368 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:17 PM PDT 24 |
| Peak memory | 206612 kb |
| Host | smart-50610bc8-b940-4f5e-85e9-51661f9ac889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945619981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1945619981 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2827039805 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 111906128 ps |
| CPU time | 1.64 seconds |
| Started | May 26 01:55:17 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 214916 kb |
| Host | smart-824b4ae7-b1a6-4715-bf5e-a522ad948dc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827039805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.2827039805 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1705743387 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 38826586 ps |
| CPU time | 1.1 seconds |
| Started | May 26 01:55:17 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 206852 kb |
| Host | smart-412d7d66-968d-4adb-87e9-e91fe713de4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705743387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.1705743387 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.89603918 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 468914721 ps |
| CPU time | 2.84 seconds |
| Started | May 26 01:55:16 PM PDT 24 |
| Finished | May 26 01:55:20 PM PDT 24 |
| Peak memory | 215504 kb |
| Host | smart-7f3a6478-6d9b-4701-bd05-9976e56dbc81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89603918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_s hadow_reg_errors_with_csr_rw.89603918 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2949222563 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 373219912 ps |
| CPU time | 2.86 seconds |
| Started | May 26 01:55:17 PM PDT 24 |
| Finished | May 26 01:55:20 PM PDT 24 |
| Peak memory | 215080 kb |
| Host | smart-7ff263ea-9154-46b1-8eaf-2ba9eb6082fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949222563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2949222563 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1522432750 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 269898627 ps |
| CPU time | 2.43 seconds |
| Started | May 26 01:55:13 PM PDT 24 |
| Finished | May 26 01:55:16 PM PDT 24 |
| Peak memory | 206700 kb |
| Host | smart-bb9bd4ec-8238-42bb-af5a-6102dd4826d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522432750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.15224 32750 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/41.kmac_intr_test.2088514381 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 19520219 ps |
| CPU time | 0.74 seconds |
| Started | May 26 01:55:44 PM PDT 24 |
| Finished | May 26 01:55:45 PM PDT 24 |
| Peak memory | 206516 kb |
| Host | smart-a88f9c05-d9bb-4235-aa11-da11b4b10b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088514381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2088514381 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.kmac_intr_test.2729722764 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 41600682 ps |
| CPU time | 0.79 seconds |
| Started | May 26 01:55:50 PM PDT 24 |
| Finished | May 26 01:55:51 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-1b1d16f9-0a47-443b-802b-24d5cc50049b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729722764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2729722764 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.kmac_intr_test.2577125518 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 17075077 ps |
| CPU time | 0.83 seconds |
| Started | May 26 01:55:45 PM PDT 24 |
| Finished | May 26 01:55:46 PM PDT 24 |
| Peak memory | 206564 kb |
| Host | smart-ebccb045-c503-40b0-ad23-c2d2c5c131e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577125518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2577125518 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.kmac_intr_test.2119060533 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 23737075 ps |
| CPU time | 0.81 seconds |
| Started | May 26 01:55:48 PM PDT 24 |
| Finished | May 26 01:55:50 PM PDT 24 |
| Peak memory | 206556 kb |
| Host | smart-6b71ded5-51f8-4e25-ade6-3f54c7c04bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119060533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2119060533 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.kmac_intr_test.1624386387 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 46138342 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:55:47 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 206560 kb |
| Host | smart-d858391c-a421-4637-bbba-6bf721683cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624386387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1624386387 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.kmac_intr_test.1329627199 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 64725769 ps |
| CPU time | 0.81 seconds |
| Started | May 26 01:55:46 PM PDT 24 |
| Finished | May 26 01:55:48 PM PDT 24 |
| Peak memory | 206448 kb |
| Host | smart-3a79b9fa-2908-4318-a911-19628e8e3e74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329627199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1329627199 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.kmac_intr_test.2953352849 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 22044832 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:55:47 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 206564 kb |
| Host | smart-ff33ab23-c845-455d-a8d4-15ebb5010b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953352849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2953352849 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.kmac_intr_test.2948600390 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 27788400 ps |
| CPU time | 0.83 seconds |
| Started | May 26 01:55:47 PM PDT 24 |
| Finished | May 26 01:55:49 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-39fc64b4-46e4-462b-98ff-6d3d70362d64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948600390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2948600390 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.kmac_intr_test.1042641363 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 35580546 ps |
| CPU time | 0.73 seconds |
| Started | May 26 01:55:44 PM PDT 24 |
| Finished | May 26 01:55:46 PM PDT 24 |
| Peak memory | 206516 kb |
| Host | smart-c8a052ad-e7ec-4fb4-b2bb-0a92f6755265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042641363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1042641363 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1259202715 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 194406692 ps |
| CPU time | 2.32 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 217052 kb |
| Host | smart-a7cdccb2-6990-4209-b59d-4ebb531a13b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259202715 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1259202715 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2771539227 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 22507258 ps |
| CPU time | 0.88 seconds |
| Started | May 26 01:55:12 PM PDT 24 |
| Finished | May 26 01:55:14 PM PDT 24 |
| Peak memory | 206552 kb |
| Host | smart-5ba5a0c0-cf6b-4ecd-aa4e-77d657b825e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771539227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2771539227 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.kmac_intr_test.101216626 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 23791370 ps |
| CPU time | 0.78 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:17 PM PDT 24 |
| Peak memory | 206484 kb |
| Host | smart-12c4ba8b-156d-447e-8d6b-76aff468e078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101216626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.101216626 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3068000390 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 145973242 ps |
| CPU time | 2.24 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 215384 kb |
| Host | smart-d6f65ccc-50af-4b1b-93a3-9fe8c6ad3dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068000390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.3068000390 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2014698065 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 57571948 ps |
| CPU time | 1.29 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:16 PM PDT 24 |
| Peak memory | 207296 kb |
| Host | smart-a3a2f045-2cd8-40c8-8ccc-5b07daa2b229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014698065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.2014698065 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2351924796 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 126788943 ps |
| CPU time | 2.09 seconds |
| Started | May 26 01:55:20 PM PDT 24 |
| Finished | May 26 01:55:22 PM PDT 24 |
| Peak memory | 215548 kb |
| Host | smart-8ffffb41-3c2f-4e00-bf53-6190e1962d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351924796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.2351924796 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2404948675 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 143954321 ps |
| CPU time | 2.76 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 223272 kb |
| Host | smart-5f7f4bd9-6de7-48a3-99a1-42d9967e0030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404948675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2404948675 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.276435920 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 239445843 ps |
| CPU time | 1.56 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 214848 kb |
| Host | smart-bca70292-00b3-40d6-bcd9-9abed793f6a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276435920 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.276435920 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.kmac_csr_rw.2303758827 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 22530304 ps |
| CPU time | 0.93 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:22 PM PDT 24 |
| Peak memory | 206496 kb |
| Host | smart-d32d56fd-56d7-4f0c-8c1a-e5c8226ab478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303758827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.2303758827 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.kmac_intr_test.1946929157 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 42341446 ps |
| CPU time | 0.88 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:23 PM PDT 24 |
| Peak memory | 206548 kb |
| Host | smart-9563d430-916a-415a-8937-934c930ad650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946929157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1946929157 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.373470332 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 67039959 ps |
| CPU time | 1.73 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:24 PM PDT 24 |
| Peak memory | 214948 kb |
| Host | smart-febbfb3f-af2f-47e4-8bc6-6199b30d4a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373470332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_ outstanding.373470332 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2715555323 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 65562001 ps |
| CPU time | 1.1 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:17 PM PDT 24 |
| Peak memory | 215540 kb |
| Host | smart-c0f2c770-f151-4564-976c-7a05d668bca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715555323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.2715555323 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1815573235 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 50217601 ps |
| CPU time | 2.45 seconds |
| Started | May 26 01:55:15 PM PDT 24 |
| Finished | May 26 01:55:19 PM PDT 24 |
| Peak memory | 223628 kb |
| Host | smart-da1a6106-9ec5-4c9d-9e3a-4dba6bc2b0ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815573235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.1815573235 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1697599958 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 534848361 ps |
| CPU time | 3.36 seconds |
| Started | May 26 01:55:16 PM PDT 24 |
| Finished | May 26 01:55:20 PM PDT 24 |
| Peak memory | 218924 kb |
| Host | smart-9036c4e7-d55f-48b6-a107-06f606d2ebcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697599958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1697599958 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3054680994 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 210053632 ps |
| CPU time | 2.53 seconds |
| Started | May 26 01:55:17 PM PDT 24 |
| Finished | May 26 01:55:20 PM PDT 24 |
| Peak memory | 206668 kb |
| Host | smart-9f229387-8198-40f0-87dc-57e4128f78f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054680994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.30546 80994 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.306334959 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 531500341 ps |
| CPU time | 2.62 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 216264 kb |
| Host | smart-0a2a00a7-46ae-471d-a25b-3389d055c7fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306334959 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.306334959 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2554805929 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 47639467 ps |
| CPU time | 1.1 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:23 PM PDT 24 |
| Peak memory | 206772 kb |
| Host | smart-d217148a-d76f-428e-8c86-83c7a2ecab4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554805929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2554805929 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.kmac_intr_test.91774473 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 40908054 ps |
| CPU time | 0.79 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:24 PM PDT 24 |
| Peak memory | 206564 kb |
| Host | smart-a8d8aa51-256a-4368-a0af-1cb2ba4d6710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91774473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.91774473 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3979896993 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 47677633 ps |
| CPU time | 1.52 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 214916 kb |
| Host | smart-18e7075c-8570-4528-86eb-d89d460f87eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979896993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.3979896993 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.4192640233 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 111771112 ps |
| CPU time | 1.05 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 215448 kb |
| Host | smart-67b79ac9-f414-4d5e-9ee3-34db9b6e6df8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192640233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.4192640233 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3045716959 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 217073341 ps |
| CPU time | 1.69 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:23 PM PDT 24 |
| Peak memory | 215024 kb |
| Host | smart-bdf1a105-71d7-4ab6-b0a7-df90ca2dfc1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045716959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.3045716959 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1559912877 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 181635106 ps |
| CPU time | 2.32 seconds |
| Started | May 26 01:55:20 PM PDT 24 |
| Finished | May 26 01:55:23 PM PDT 24 |
| Peak memory | 215116 kb |
| Host | smart-61b217cb-4a1d-4c21-88f5-98c116a5f8e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559912877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1559912877 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.615286971 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 252206910 ps |
| CPU time | 4.72 seconds |
| Started | May 26 01:55:20 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 206720 kb |
| Host | smart-6fb796e0-47ba-47af-9930-718072ac889d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615286971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.615286 971 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.461099910 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 130880576 ps |
| CPU time | 2.24 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 216812 kb |
| Host | smart-b53ced42-496c-46a5-92cf-3d161d3123ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461099910 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.461099910 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2555593668 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 25493665 ps |
| CPU time | 0.96 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 206520 kb |
| Host | smart-6317cc21-9086-4c49-a6af-e1f2f103ab0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555593668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2555593668 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.kmac_intr_test.2706076126 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 37877284 ps |
| CPU time | 0.79 seconds |
| Started | May 26 01:55:25 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-3f013c2a-852c-4dc3-bb0c-597624451184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706076126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2706076126 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2193093438 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 347611850 ps |
| CPU time | 2.6 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 214864 kb |
| Host | smart-51496a91-18f4-43c5-b83e-46663adbf77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193093438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.2193093438 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2574528926 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 84933051 ps |
| CPU time | 0.97 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 215188 kb |
| Host | smart-8ddfb2b4-46fe-4ef0-9a6c-4706bac612f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574528926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.2574528926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2632333663 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 36564794 ps |
| CPU time | 1.76 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:24 PM PDT 24 |
| Peak memory | 215380 kb |
| Host | smart-241bf41b-5765-43e7-abbf-3f74e5417b36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632333663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.2632333663 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1744342338 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 98146158 ps |
| CPU time | 2.71 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 215096 kb |
| Host | smart-33e079a6-dc9c-4ae1-b644-6c01154deed3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744342338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1744342338 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1506761368 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 379950770 ps |
| CPU time | 2.97 seconds |
| Started | May 26 01:55:20 PM PDT 24 |
| Finished | May 26 01:55:24 PM PDT 24 |
| Peak memory | 214980 kb |
| Host | smart-264d1829-17fa-46e9-ad9d-53fb1fd24959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506761368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.15067 61368 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3825866981 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 296741576 ps |
| CPU time | 2.58 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:24 PM PDT 24 |
| Peak memory | 216424 kb |
| Host | smart-8d53608f-e3e5-4cb7-9dc2-a70bd9857b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825866981 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3825866981 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.kmac_csr_rw.2220110438 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 21584459 ps |
| CPU time | 0.93 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:24 PM PDT 24 |
| Peak memory | 206504 kb |
| Host | smart-d5465a62-9504-4a8f-99bc-61f3c5d5dd15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220110438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2220110438 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.kmac_intr_test.2327412169 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 37304982 ps |
| CPU time | 0.75 seconds |
| Started | May 26 01:55:21 PM PDT 24 |
| Finished | May 26 01:55:23 PM PDT 24 |
| Peak memory | 206556 kb |
| Host | smart-3b9c7e92-ea9a-4755-ac73-0fb71236a94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327412169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2327412169 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3187353443 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 78228242 ps |
| CPU time | 1.39 seconds |
| Started | May 26 01:55:22 PM PDT 24 |
| Finished | May 26 01:55:25 PM PDT 24 |
| Peak memory | 215232 kb |
| Host | smart-c71bb447-1fb9-423b-a17a-a1dd9c68512e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187353443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.3187353443 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1023172918 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 47221242 ps |
| CPU time | 1.12 seconds |
| Started | May 26 01:55:24 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 215508 kb |
| Host | smart-884e2422-a1a0-46f2-ab77-101b694e4796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023172918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.1023172918 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_shadow_reg_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.537173374 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 604906270 ps |
| CPU time | 2.11 seconds |
| Started | May 26 01:55:24 PM PDT 24 |
| Finished | May 26 01:55:27 PM PDT 24 |
| Peak memory | 215472 kb |
| Host | smart-1aecce7c-5fb1-45e6-b7c0-0162cf5ca648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537173374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_ shadow_reg_errors_with_csr_rw.537173374 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.kmac_tl_errors.648358456 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 395854818 ps |
| CPU time | 2.48 seconds |
| Started | May 26 01:55:23 PM PDT 24 |
| Finished | May 26 01:55:26 PM PDT 24 |
| Peak memory | 214996 kb |
| Host | smart-1106eaa8-b29e-4b31-9d74-4a47880310ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648358456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.648358456 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3053379147 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 330250344 ps |
| CPU time | 4.07 seconds |
| Started | May 26 01:55:25 PM PDT 24 |
| Finished | May 26 01:55:30 PM PDT 24 |
| Peak memory | 215024 kb |
| Host | smart-a92bea20-020d-419f-a564-73a0b3b64147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053379147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.30533 79147 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.kmac_alert_test.3280906021 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 28334945 ps |
| CPU time | 0.81 seconds |
| Started | May 26 02:54:54 PM PDT 24 |
| Finished | May 26 02:54:58 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-6762379e-75c8-4deb-b5e4-7a059763face |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280906021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3280906021 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/0.kmac_app.322818156 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 13400029802 ps |
| CPU time | 163.38 seconds |
| Started | May 26 02:54:59 PM PDT 24 |
| Finished | May 26 02:57:46 PM PDT 24 |
| Peak memory | 235936 kb |
| Host | smart-34f39160-d27c-412e-9f03-83413c1e9333 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322818156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.322818156 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_app/latest |
| Test location | /workspace/coverage/default/0.kmac_app_with_partial_data.3551095985 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 8513896771 ps |
| CPU time | 180.66 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 02:58:04 PM PDT 24 |
| Peak memory | 236832 kb |
| Host | smart-af75c9ce-fb62-4101-8f61-7af0be8c8d9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551095985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3551095985 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/0.kmac_burst_write.3569813018 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 134381930013 ps |
| CPU time | 810.73 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 03:08:34 PM PDT 24 |
| Peak memory | 230484 kb |
| Host | smart-fb11c9dc-2df5-4d1c-867a-9148247755bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569813018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3569813018 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/0.kmac_edn_timeout_error.2910098891 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 546709985 ps |
| CPU time | 8.74 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 02:55:09 PM PDT 24 |
| Peak memory | 220244 kb |
| Host | smart-9fcbe4ff-20c0-4cec-a092-dd10b56462c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2910098891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2910098891 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/0.kmac_entropy_mode_error.2427661887 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1055273631 ps |
| CPU time | 6.29 seconds |
| Started | May 26 02:54:56 PM PDT 24 |
| Finished | May 26 02:55:06 PM PDT 24 |
| Peak memory | 221200 kb |
| Host | smart-e6ae446a-209d-4013-b110-be8bf4f3c812 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2427661887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2427661887 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/0.kmac_entropy_ready_error.3318220266 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 19847769623 ps |
| CPU time | 15.86 seconds |
| Started | May 26 02:54:53 PM PDT 24 |
| Finished | May 26 02:55:12 PM PDT 24 |
| Peak memory | 215512 kb |
| Host | smart-c87a7ad9-ef0e-442b-8659-f28b6325d67f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3318220266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3318220266 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/0.kmac_entropy_refresh.4074704371 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 13539672732 ps |
| CPU time | 257.54 seconds |
| Started | May 26 02:55:03 PM PDT 24 |
| Finished | May 26 02:59:24 PM PDT 24 |
| Peak memory | 241572 kb |
| Host | smart-9da95f79-b339-4109-a5b7-9fe8c097dfa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074704371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.4074704371 +enable_masking=0 +s w_key_masked=0 |
| Directory | /workspace/0.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/0.kmac_error.3147828319 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2807175696 ps |
| CPU time | 204.92 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 02:58:26 PM PDT 24 |
| Peak memory | 248388 kb |
| Host | smart-32f5df08-0111-4f23-b26d-8c2910fd2936 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147828319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3147828319 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_error/latest |
| Test location | /workspace/coverage/default/0.kmac_key_error.447058087 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 1558352277 ps |
| CPU time | 7.84 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 02:55:12 PM PDT 24 |
| Peak memory | 207148 kb |
| Host | smart-1fd90eec-b3f1-4cd7-b86f-b76c4199e7ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447058087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.447058087 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_key_error/latest |
| Test location | /workspace/coverage/default/0.kmac_lc_escalation.2572900027 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2915446378 ps |
| CPU time | 13 seconds |
| Started | May 26 02:55:03 PM PDT 24 |
| Finished | May 26 02:55:19 PM PDT 24 |
| Peak memory | 231928 kb |
| Host | smart-7c8767ad-8137-49f5-9534-2f6a07063797 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572900027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2572900027 +enable_masking=0 +sw_ke y_masked=0 |
| Directory | /workspace/0.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/0.kmac_long_msg_and_output.2919281336 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 8601620719 ps |
| CPU time | 256.65 seconds |
| Started | May 26 02:54:56 PM PDT 24 |
| Finished | May 26 02:59:16 PM PDT 24 |
| Peak memory | 241104 kb |
| Host | smart-212189e9-51b6-4d22-95f6-7daa571c0fde |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919281336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.2919281336 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/0.kmac_mubi.2036471396 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2145620293 ps |
| CPU time | 70.6 seconds |
| Started | May 26 02:54:54 PM PDT 24 |
| Finished | May 26 02:56:07 PM PDT 24 |
| Peak memory | 226996 kb |
| Host | smart-dfa68cc2-fb56-41e5-94bf-27e7bd9a1d44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036471396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2036471396 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_mubi/latest |
| Test location | /workspace/coverage/default/0.kmac_sec_cm.2460888875 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4968692003 ps |
| CPU time | 26.47 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 02:55:28 PM PDT 24 |
| Peak memory | 252088 kb |
| Host | smart-9820e197-d0f7-4660-804d-7ca2e28ef062 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460888875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2460888875 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_sec_cm/latest |
| Test location | /workspace/coverage/default/0.kmac_sideload.2109769864 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 4881729446 ps |
| CPU time | 66.94 seconds |
| Started | May 26 02:54:56 PM PDT 24 |
| Finished | May 26 02:56:06 PM PDT 24 |
| Peak memory | 224240 kb |
| Host | smart-296ca627-3a8e-4cb0-8ec3-93222c9058de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109769864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2109769864 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_sideload/latest |
| Test location | /workspace/coverage/default/0.kmac_smoke.2244774913 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 697606589 ps |
| CPU time | 18.31 seconds |
| Started | May 26 02:54:56 PM PDT 24 |
| Finished | May 26 02:55:17 PM PDT 24 |
| Peak memory | 223672 kb |
| Host | smart-029acc17-1cd1-43cb-8771-169877f0c84b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244774913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2244774913 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_smoke/latest |
| Test location | /workspace/coverage/default/0.kmac_stress_all.22523893 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7932257517 ps |
| CPU time | 132.28 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 02:57:17 PM PDT 24 |
| Peak memory | 252732 kb |
| Host | smart-d3ee2e6e-3433-4158-a41f-8d7ca7a82d5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=22523893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.22523893 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/0.kmac_test_vectors_kmac.2060244113 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 235431207 ps |
| CPU time | 4.84 seconds |
| Started | May 26 02:54:54 PM PDT 24 |
| Finished | May 26 02:55:02 PM PDT 24 |
| Peak memory | 215532 kb |
| Host | smart-160821e7-8c6c-4e29-bb51-1987a682addf |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060244113 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.kmac_test_vectors_kmac.2060244113 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.1553720849 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 67613957 ps |
| CPU time | 4.05 seconds |
| Started | May 26 02:54:51 PM PDT 24 |
| Finished | May 26 02:54:58 PM PDT 24 |
| Peak memory | 215604 kb |
| Host | smart-143a127f-3b2f-4111-8a2a-8c9bacee883c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553720849 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1553720849 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/0.kmac_test_vectors_sha3_224.508088173 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 18390797849 ps |
| CPU time | 1535.38 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 03:20:40 PM PDT 24 |
| Peak memory | 375344 kb |
| Host | smart-a68cb70f-1fd6-4120-838d-bdd5eb1814d7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=508088173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.508088173 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/0.kmac_test_vectors_sha3_256.2559045514 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 181710336938 ps |
| CPU time | 1850.22 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 03:25:54 PM PDT 24 |
| Peak memory | 371692 kb |
| Host | smart-0d7a56fc-2a5c-48b6-bee9-ddea45cfb158 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2559045514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2559045514 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/0.kmac_test_vectors_sha3_384.469692320 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 48759691750 ps |
| CPU time | 1309.4 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 03:16:51 PM PDT 24 |
| Peak memory | 331528 kb |
| Host | smart-c9f4539a-645d-460d-b41f-bec2381a032e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=469692320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.469692320 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/0.kmac_test_vectors_sha3_512.1552530551 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 32121424256 ps |
| CPU time | 874.66 seconds |
| Started | May 26 02:54:56 PM PDT 24 |
| Finished | May 26 03:09:34 PM PDT 24 |
| Peak memory | 291552 kb |
| Host | smart-25e4345c-16ce-4dd1-b4d1-b860c303ee30 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1552530551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1552530551 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/0.kmac_test_vectors_shake_128.3252931821 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 515657247507 ps |
| CPU time | 5322.39 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 04:23:51 PM PDT 24 |
| Peak memory | 634792 kb |
| Host | smart-205b6127-2a28-44b8-add1-cacb2c2ea386 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3252931821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3252931821 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/0.kmac_test_vectors_shake_256.488833387 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 44361724864 ps |
| CPU time | 3493.02 seconds |
| Started | May 26 02:54:56 PM PDT 24 |
| Finished | May 26 03:53:13 PM PDT 24 |
| Peak memory | 556088 kb |
| Host | smart-146d2a9e-9e32-4c43-bb2c-ab4264885edb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=488833387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.488833387 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/1.kmac_alert_test.2319826322 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 40052735 ps |
| CPU time | 0.8 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 02:55:04 PM PDT 24 |
| Peak memory | 204824 kb |
| Host | smart-c2031cb1-43c0-4550-8f58-04bb3e11d541 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319826322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2319826322 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/1.kmac_app_with_partial_data.3237401848 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 18022614002 ps |
| CPU time | 243.91 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 02:59:04 PM PDT 24 |
| Peak memory | 242872 kb |
| Host | smart-d3df84de-7e6e-4be0-9540-86c653652307 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237401848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.3237401848 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/1.kmac_burst_write.2663772846 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 19814094444 ps |
| CPU time | 387.6 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 03:01:29 PM PDT 24 |
| Peak memory | 228672 kb |
| Host | smart-afbd27f9-fd20-4dad-8ed7-a12e71eb0b47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663772846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2663772846 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/1.kmac_edn_timeout_error.1891581368 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1818401942 ps |
| CPU time | 37.55 seconds |
| Started | May 26 02:54:56 PM PDT 24 |
| Finished | May 26 02:55:36 PM PDT 24 |
| Peak memory | 223404 kb |
| Host | smart-96229ef9-6a8f-4dc9-a11d-ae5ac1ebfefd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1891581368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1891581368 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/1.kmac_entropy_mode_error.1988135307 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 454726059 ps |
| CPU time | 21.19 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 02:55:25 PM PDT 24 |
| Peak memory | 231164 kb |
| Host | smart-7a20170e-88bb-4de4-9724-1cbf08b292fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1988135307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1988135307 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/1.kmac_entropy_ready_error.1532837713 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 121780737772 ps |
| CPU time | 76.23 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 02:56:17 PM PDT 24 |
| Peak memory | 223668 kb |
| Host | smart-668b6635-23e0-4178-8aba-10dfdcb7402c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532837713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1532837713 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/1.kmac_entropy_refresh.178316808 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 16554385960 ps |
| CPU time | 212.81 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 02:58:33 PM PDT 24 |
| Peak memory | 239364 kb |
| Host | smart-c09e4d28-bf4f-4c96-85c7-d300b4056094 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178316808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.178316808 +enable_masking=0 +sw_ key_masked=0 |
| Directory | /workspace/1.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/1.kmac_error.309395886 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 43017970450 ps |
| CPU time | 277.67 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 02:59:39 PM PDT 24 |
| Peak memory | 252944 kb |
| Host | smart-6ce064d1-781d-43d6-95f1-2a902309d2bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309395886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.309395886 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_error/latest |
| Test location | /workspace/coverage/default/1.kmac_long_msg_and_output.3728078414 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 31394523461 ps |
| CPU time | 705.49 seconds |
| Started | May 26 02:54:53 PM PDT 24 |
| Finished | May 26 03:06:42 PM PDT 24 |
| Peak memory | 281628 kb |
| Host | smart-b345c428-79e3-48f0-8d5f-5a7e97b56e46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728078414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.3728078414 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/1.kmac_mubi.2533315006 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 4173996293 ps |
| CPU time | 221.54 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 02:58:43 PM PDT 24 |
| Peak memory | 243320 kb |
| Host | smart-5bd4b16f-c1ce-4e10-82ea-fa592bb341ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533315006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2533315006 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_mubi/latest |
| Test location | /workspace/coverage/default/1.kmac_sec_cm.4282377358 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 16637249639 ps |
| CPU time | 47.77 seconds |
| Started | May 26 02:54:56 PM PDT 24 |
| Finished | May 26 02:55:47 PM PDT 24 |
| Peak memory | 251844 kb |
| Host | smart-78c04ec8-f867-4c8e-bf31-5698480a93bf |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282377358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.4282377358 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_sec_cm/latest |
| Test location | /workspace/coverage/default/1.kmac_sideload.4028898101 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2531203327 ps |
| CPU time | 182.57 seconds |
| Started | May 26 02:54:59 PM PDT 24 |
| Finished | May 26 02:58:06 PM PDT 24 |
| Peak memory | 238024 kb |
| Host | smart-c19a420e-bb48-4188-a0e0-245df88eef55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028898101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.4028898101 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_sideload/latest |
| Test location | /workspace/coverage/default/1.kmac_smoke.575496052 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2736394819 ps |
| CPU time | 45.75 seconds |
| Started | May 26 02:54:55 PM PDT 24 |
| Finished | May 26 02:55:43 PM PDT 24 |
| Peak memory | 215980 kb |
| Host | smart-7d84c23b-8f5d-47d3-bb0a-fc58e82b9567 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575496052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.575496052 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_smoke/latest |
| Test location | /workspace/coverage/default/1.kmac_stress_all.3863595634 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 9303740257 ps |
| CPU time | 471.18 seconds |
| Started | May 26 02:54:55 PM PDT 24 |
| Finished | May 26 03:02:50 PM PDT 24 |
| Peak memory | 306220 kb |
| Host | smart-9489334c-26c6-40c2-8707-8bbfab5edddf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3863595634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3863595634 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/1.kmac_test_vectors_kmac.3176903513 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 367378950 ps |
| CPU time | 4.15 seconds |
| Started | May 26 02:54:59 PM PDT 24 |
| Finished | May 26 02:55:07 PM PDT 24 |
| Peak memory | 215524 kb |
| Host | smart-ac513deb-58d2-4695-8199-e0e93fb1f8ae |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176903513 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.kmac_test_vectors_kmac.3176903513 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1499425342 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 62779066 ps |
| CPU time | 4.16 seconds |
| Started | May 26 02:54:49 PM PDT 24 |
| Finished | May 26 02:54:56 PM PDT 24 |
| Peak memory | 215508 kb |
| Host | smart-09aea5fc-3a58-4c03-afba-53b392995d6c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499425342 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1499425342 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/1.kmac_test_vectors_sha3_224.3127617613 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 19774999227 ps |
| CPU time | 1517.08 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 03:20:21 PM PDT 24 |
| Peak memory | 391448 kb |
| Host | smart-a2ee6c45-dd18-41bd-96c6-40c7f58330b1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3127617613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3127617613 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/1.kmac_test_vectors_sha3_256.1154858392 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 76722881774 ps |
| CPU time | 1400.7 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 03:18:23 PM PDT 24 |
| Peak memory | 372492 kb |
| Host | smart-eaab2a77-e2ca-429e-a5ea-49c0fb83ab7c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1154858392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1154858392 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/1.kmac_test_vectors_sha3_384.4067849198 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 96263803404 ps |
| CPU time | 1339.9 seconds |
| Started | May 26 02:54:59 PM PDT 24 |
| Finished | May 26 03:17:23 PM PDT 24 |
| Peak memory | 336240 kb |
| Host | smart-886dac1d-a488-44aa-9f1a-f06437c56d15 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4067849198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.4067849198 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/1.kmac_test_vectors_sha3_512.4254582771 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 201966780868 ps |
| CPU time | 967.06 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 03:11:09 PM PDT 24 |
| Peak memory | 293424 kb |
| Host | smart-1b9b4421-35a7-4d90-a9f6-ee90497026bb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4254582771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.4254582771 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/1.kmac_test_vectors_shake_128.576336558 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 730681843765 ps |
| CPU time | 4392.7 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 04:08:14 PM PDT 24 |
| Peak memory | 655220 kb |
| Host | smart-f3a46ec0-8124-40fd-bf29-9abc69ec174a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=576336558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.576336558 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/1.kmac_test_vectors_shake_256.753267448 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 42879789628 ps |
| CPU time | 3382.61 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 03:51:24 PM PDT 24 |
| Peak memory | 544216 kb |
| Host | smart-ece4862b-6a1d-4c54-a54b-eb2720902b27 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=753267448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.753267448 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/10.kmac_alert_test.2739944633 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 21734517 ps |
| CPU time | 0.8 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 02:55:40 PM PDT 24 |
| Peak memory | 204852 kb |
| Host | smart-33e0e641-c5d7-4ecf-a2f1-5f92d61b3448 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739944633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2739944633 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/10.kmac_app.353560922 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 4343234053 ps |
| CPU time | 49.92 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 02:56:28 PM PDT 24 |
| Peak memory | 223876 kb |
| Host | smart-1d6c97b8-d132-49cd-80b9-a8b2ad4b472e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353560922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.353560922 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_app/latest |
| Test location | /workspace/coverage/default/10.kmac_burst_write.2587626726 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 8925655160 ps |
| CPU time | 111.56 seconds |
| Started | May 26 02:55:21 PM PDT 24 |
| Finished | May 26 02:57:15 PM PDT 24 |
| Peak memory | 223720 kb |
| Host | smart-9e01883e-8395-4a00-93e0-32040a897118 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587626726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2587626726 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/10.kmac_edn_timeout_error.2054803741 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1786305469 ps |
| CPU time | 31.33 seconds |
| Started | May 26 02:55:30 PM PDT 24 |
| Finished | May 26 02:56:03 PM PDT 24 |
| Peak memory | 223424 kb |
| Host | smart-2d66d974-058d-4b2a-a6f9-77269cafdaf3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2054803741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2054803741 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/10.kmac_entropy_mode_error.1397984952 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 131647474 ps |
| CPU time | 4.48 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 02:55:44 PM PDT 24 |
| Peak memory | 218260 kb |
| Host | smart-f3504f53-ba36-4cc5-9f1f-2d3a42887b9b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1397984952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1397984952 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/10.kmac_entropy_refresh.3499197053 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 13327691590 ps |
| CPU time | 151.75 seconds |
| Started | May 26 02:55:36 PM PDT 24 |
| Finished | May 26 02:58:09 PM PDT 24 |
| Peak memory | 234984 kb |
| Host | smart-b132c93c-dce2-46be-be02-42379bf94746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499197053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3499197053 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/10.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/10.kmac_error.3200358336 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 23461726481 ps |
| CPU time | 127.15 seconds |
| Started | May 26 02:55:30 PM PDT 24 |
| Finished | May 26 02:57:39 PM PDT 24 |
| Peak memory | 237896 kb |
| Host | smart-a03c643f-356f-434b-a9b5-62b4c7ad6a5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200358336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3200358336 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_error/latest |
| Test location | /workspace/coverage/default/10.kmac_key_error.3016631866 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2125905999 ps |
| CPU time | 4.1 seconds |
| Started | May 26 02:55:46 PM PDT 24 |
| Finished | May 26 02:55:50 PM PDT 24 |
| Peak memory | 207076 kb |
| Host | smart-8eb4dd61-57c0-4d16-b48b-a29ac0a89a5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016631866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3016631866 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_key_error/latest |
| Test location | /workspace/coverage/default/10.kmac_lc_escalation.328320135 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 5442863454 ps |
| CPU time | 10.22 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 02:55:48 PM PDT 24 |
| Peak memory | 222144 kb |
| Host | smart-965f3789-0f25-4e1c-8e05-7ce4c7a80597 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328320135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.328320135 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/10.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/10.kmac_long_msg_and_output.354429975 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 97173432926 ps |
| CPU time | 1097.82 seconds |
| Started | May 26 02:55:29 PM PDT 24 |
| Finished | May 26 03:13:48 PM PDT 24 |
| Peak memory | 322788 kb |
| Host | smart-c3316515-84ab-4dec-a69d-62d9a947f182 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354429975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_an d_output.354429975 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/10.kmac_sideload.2576292284 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 14774646410 ps |
| CPU time | 293.45 seconds |
| Started | May 26 02:55:22 PM PDT 24 |
| Finished | May 26 03:00:17 PM PDT 24 |
| Peak memory | 241668 kb |
| Host | smart-3c4a5f5d-7486-4f92-bfc7-ba1d0211bb72 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576292284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2576292284 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_sideload/latest |
| Test location | /workspace/coverage/default/10.kmac_smoke.1612569206 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5870454617 ps |
| CPU time | 30.62 seconds |
| Started | May 26 02:55:22 PM PDT 24 |
| Finished | May 26 02:55:54 PM PDT 24 |
| Peak memory | 218656 kb |
| Host | smart-fed23d01-7c0a-48d1-8fc2-6380ab73e121 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612569206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1612569206 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_smoke/latest |
| Test location | /workspace/coverage/default/10.kmac_stress_all.3071029792 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 47543022832 ps |
| CPU time | 721.31 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 03:07:42 PM PDT 24 |
| Peak memory | 300408 kb |
| Host | smart-ec042796-9676-4dd4-aa85-638ef0b2b1f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3071029792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3071029792 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/10.kmac_test_vectors_kmac.2302986654 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 280834157 ps |
| CPU time | 4.14 seconds |
| Started | May 26 02:55:44 PM PDT 24 |
| Finished | May 26 02:55:49 PM PDT 24 |
| Peak memory | 215596 kb |
| Host | smart-cd219f99-3aca-4477-9b06-d11ee4784f77 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302986654 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.kmac_test_vectors_kmac.2302986654 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.865312611 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 127779121 ps |
| CPU time | 4.05 seconds |
| Started | May 26 02:55:30 PM PDT 24 |
| Finished | May 26 02:55:35 PM PDT 24 |
| Peak memory | 208580 kb |
| Host | smart-32ac20a1-ec60-48b1-b0e1-c4c38ed83809 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865312611 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 10.kmac_test_vectors_kmac_xof.865312611 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/10.kmac_test_vectors_sha3_224.996501022 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 18888004366 ps |
| CPU time | 1413.75 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 03:19:13 PM PDT 24 |
| Peak memory | 392920 kb |
| Host | smart-9c94a456-2d66-45fe-bd4a-dd0d51eb330e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=996501022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.996501022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/10.kmac_test_vectors_sha3_256.356509957 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 72438374573 ps |
| CPU time | 1436.78 seconds |
| Started | May 26 02:55:30 PM PDT 24 |
| Finished | May 26 03:19:28 PM PDT 24 |
| Peak memory | 366856 kb |
| Host | smart-995a554c-d0ad-448a-900d-b9c13acdfff8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=356509957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.356509957 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/10.kmac_test_vectors_sha3_384.19437772 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 97348413176 ps |
| CPU time | 1297.53 seconds |
| Started | May 26 02:55:31 PM PDT 24 |
| Finished | May 26 03:17:10 PM PDT 24 |
| Peak memory | 333668 kb |
| Host | smart-0f1c1e2d-22f3-458a-8026-bd81c816ea02 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=19437772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.19437772 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/10.kmac_test_vectors_sha3_512.547592168 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 100570174161 ps |
| CPU time | 1015.59 seconds |
| Started | May 26 02:55:31 PM PDT 24 |
| Finished | May 26 03:12:28 PM PDT 24 |
| Peak memory | 296564 kb |
| Host | smart-15ee2cde-c244-45e3-ae15-b148132412dc |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=547592168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.547592168 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/10.kmac_test_vectors_shake_128.1382453334 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 107781127882 ps |
| CPU time | 3866.76 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 04:00:07 PM PDT 24 |
| Peak memory | 623860 kb |
| Host | smart-f6f35143-748c-445c-b7d2-9f1e7626bc14 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1382453334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.1382453334 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/10.kmac_test_vectors_shake_256.939474598 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 186977589358 ps |
| CPU time | 3401.76 seconds |
| Started | May 26 02:55:29 PM PDT 24 |
| Finished | May 26 03:52:13 PM PDT 24 |
| Peak memory | 556428 kb |
| Host | smart-511b11f4-081f-426e-916a-bc023726fccd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=939474598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.939474598 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/10.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/11.kmac_app.2263678960 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 6368432418 ps |
| CPU time | 115.31 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 02:57:34 PM PDT 24 |
| Peak memory | 230912 kb |
| Host | smart-5cf19cf1-11ab-4ce2-ab32-6b922e48324d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263678960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2263678960 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_app/latest |
| Test location | /workspace/coverage/default/11.kmac_burst_write.3956708814 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 8381618139 ps |
| CPU time | 679.78 seconds |
| Started | May 26 02:55:28 PM PDT 24 |
| Finished | May 26 03:06:49 PM PDT 24 |
| Peak memory | 232420 kb |
| Host | smart-22b3663b-b8d3-40e7-920d-71bcfc278bbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956708814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3956708814 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/11.kmac_edn_timeout_error.3222489761 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 13046975063 ps |
| CPU time | 16.23 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 02:55:56 PM PDT 24 |
| Peak memory | 223460 kb |
| Host | smart-9caa0c82-041f-487b-9b79-4c15107fbc44 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3222489761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3222489761 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/11.kmac_entropy_mode_error.826520915 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 688144457 ps |
| CPU time | 18.46 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 02:55:59 PM PDT 24 |
| Peak memory | 223144 kb |
| Host | smart-4c438157-a547-4ac1-9051-2c244bc041c9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=826520915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.826520915 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/11.kmac_entropy_refresh.2213431813 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 6692164304 ps |
| CPU time | 33.9 seconds |
| Started | May 26 02:55:40 PM PDT 24 |
| Finished | May 26 02:56:15 PM PDT 24 |
| Peak memory | 223820 kb |
| Host | smart-a3f9ca51-4fd6-4074-a033-f7bcda92066f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213431813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.2213431813 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/11.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/11.kmac_error.3550302151 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 8567154176 ps |
| CPU time | 111.97 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 02:57:31 PM PDT 24 |
| Peak memory | 238196 kb |
| Host | smart-a817cb33-1aea-4cb3-96cd-c808a499766f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550302151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3550302151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_error/latest |
| Test location | /workspace/coverage/default/11.kmac_key_error.4166187276 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1755952266 ps |
| CPU time | 9.62 seconds |
| Started | May 26 02:55:43 PM PDT 24 |
| Finished | May 26 02:55:54 PM PDT 24 |
| Peak memory | 207116 kb |
| Host | smart-1d050378-beb0-4355-aa61-2eafc0ce2e68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166187276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.4166187276 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_key_error/latest |
| Test location | /workspace/coverage/default/11.kmac_lc_escalation.3546375321 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 66864590 ps |
| CPU time | 1.33 seconds |
| Started | May 26 02:55:41 PM PDT 24 |
| Finished | May 26 02:55:44 PM PDT 24 |
| Peak memory | 219600 kb |
| Host | smart-6a93f98e-fa26-4136-a59a-f3d6e6463804 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546375321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3546375321 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/11.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/11.kmac_long_msg_and_output.1551988014 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 50839455301 ps |
| CPU time | 726.41 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 03:07:47 PM PDT 24 |
| Peak memory | 288268 kb |
| Host | smart-d06ac5a2-b86b-4c04-9958-6c94178cbace |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551988014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a nd_output.1551988014 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/11.kmac_sideload.3627238214 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 7791020229 ps |
| CPU time | 216.99 seconds |
| Started | May 26 02:55:34 PM PDT 24 |
| Finished | May 26 02:59:12 PM PDT 24 |
| Peak memory | 241072 kb |
| Host | smart-287c2d3d-fbba-4b92-9180-2dc8867829e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627238214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3627238214 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_sideload/latest |
| Test location | /workspace/coverage/default/11.kmac_smoke.2456566499 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2709735381 ps |
| CPU time | 43.37 seconds |
| Started | May 26 02:55:29 PM PDT 24 |
| Finished | May 26 02:56:13 PM PDT 24 |
| Peak memory | 221788 kb |
| Host | smart-f856a35f-76ed-4389-95b5-681dd52f7d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456566499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2456566499 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_smoke/latest |
| Test location | /workspace/coverage/default/11.kmac_stress_all.1653551598 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 4950635557 ps |
| CPU time | 171.43 seconds |
| Started | May 26 02:55:41 PM PDT 24 |
| Finished | May 26 02:58:34 PM PDT 24 |
| Peak memory | 265720 kb |
| Host | smart-5ed749c6-f78c-40c4-82c0-acf7cfa7fe1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1653551598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1653551598 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/11.kmac_test_vectors_kmac.3849888551 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 69172290 ps |
| CPU time | 3.92 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 02:55:43 PM PDT 24 |
| Peak memory | 215476 kb |
| Host | smart-919b30d9-d42d-4934-852e-9af60a679db8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849888551 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.kmac_test_vectors_kmac.3849888551 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.468176529 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 130341185 ps |
| CPU time | 4.06 seconds |
| Started | May 26 02:55:30 PM PDT 24 |
| Finished | May 26 02:55:35 PM PDT 24 |
| Peak memory | 215524 kb |
| Host | smart-884f07ff-3c32-4459-a84a-daa889ebcf3d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468176529 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.kmac_test_vectors_kmac_xof.468176529 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/11.kmac_test_vectors_sha3_224.2427642521 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 167513555365 ps |
| CPU time | 1876.47 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 03:26:55 PM PDT 24 |
| Peak memory | 389964 kb |
| Host | smart-54fbe614-d316-4fba-99f3-a4a9c3c00900 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2427642521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.2427642521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/11.kmac_test_vectors_sha3_256.2911619079 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 60587428984 ps |
| CPU time | 1583.75 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 03:22:05 PM PDT 24 |
| Peak memory | 370968 kb |
| Host | smart-45fa6b50-e50c-4f5b-8ee5-c1b2e999b351 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2911619079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.2911619079 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/11.kmac_test_vectors_sha3_384.1913581874 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 13847677115 ps |
| CPU time | 1084.25 seconds |
| Started | May 26 02:55:34 PM PDT 24 |
| Finished | May 26 03:13:39 PM PDT 24 |
| Peak memory | 336584 kb |
| Host | smart-bace3f70-4399-4ada-9c26-b54f384e48fd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1913581874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.1913581874 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/11.kmac_test_vectors_sha3_512.2703384801 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 41598427289 ps |
| CPU time | 812.51 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 03:09:13 PM PDT 24 |
| Peak memory | 296268 kb |
| Host | smart-12e864a3-f510-4340-b9fd-7005f53cf335 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2703384801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.2703384801 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/11.kmac_test_vectors_shake_128.736106624 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 193528703222 ps |
| CPU time | 5010.51 seconds |
| Started | May 26 02:55:43 PM PDT 24 |
| Finished | May 26 04:19:15 PM PDT 24 |
| Peak memory | 650696 kb |
| Host | smart-ff17381c-c7c9-4aba-856d-6b78745c18c2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=736106624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.736106624 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/11.kmac_test_vectors_shake_256.1886131632 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 223692950947 ps |
| CPU time | 4343.95 seconds |
| Started | May 26 02:55:46 PM PDT 24 |
| Finished | May 26 04:08:11 PM PDT 24 |
| Peak memory | 561200 kb |
| Host | smart-d2649c0d-f543-4f8e-adfd-94eaadd87c83 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1886131632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1886131632 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/11.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/12.kmac_alert_test.2164708490 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 18100739 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:55:46 PM PDT 24 |
| Finished | May 26 02:55:47 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-fd283c5d-e43d-4a28-8d55-18e47618ddd7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164708490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2164708490 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/12.kmac_app.1445385501 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 9861323275 ps |
| CPU time | 90.34 seconds |
| Started | May 26 02:55:43 PM PDT 24 |
| Finished | May 26 02:57:14 PM PDT 24 |
| Peak memory | 229288 kb |
| Host | smart-d74ffc2e-459d-49fa-93bc-4caaf3aa04c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445385501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1445385501 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_app/latest |
| Test location | /workspace/coverage/default/12.kmac_burst_write.483050291 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 19883363898 ps |
| CPU time | 223.47 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 02:59:24 PM PDT 24 |
| Peak memory | 225336 kb |
| Host | smart-1d01b355-027e-4ad9-84c2-e8d0419258d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=483050291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.483050291 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/12.kmac_edn_timeout_error.307336402 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 175784269 ps |
| CPU time | 12.86 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 02:55:54 PM PDT 24 |
| Peak memory | 223440 kb |
| Host | smart-527302a3-d0ed-430f-8fba-45ad2d7190b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=307336402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.307336402 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/12.kmac_entropy_mode_error.779443777 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 4656285179 ps |
| CPU time | 30.05 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 02:56:11 PM PDT 24 |
| Peak memory | 223488 kb |
| Host | smart-06aac677-0e28-49b1-8eec-10efff932ab7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=779443777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.779443777 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/12.kmac_entropy_refresh.3468743473 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 23888568237 ps |
| CPU time | 86.52 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 02:57:05 PM PDT 24 |
| Peak memory | 227924 kb |
| Host | smart-6305f2a9-7910-45e8-81c8-c46c2bccf3c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468743473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3468743473 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/12.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/12.kmac_error.3971571426 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 6475265574 ps |
| CPU time | 168.39 seconds |
| Started | May 26 02:55:42 PM PDT 24 |
| Finished | May 26 02:58:32 PM PDT 24 |
| Peak memory | 240116 kb |
| Host | smart-abb03ee9-1282-4080-98b8-911eb9418516 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3971571426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3971571426 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_error/latest |
| Test location | /workspace/coverage/default/12.kmac_key_error.3297782881 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1193263386 ps |
| CPU time | 2.12 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 02:55:41 PM PDT 24 |
| Peak memory | 215292 kb |
| Host | smart-196c8615-7861-4133-b5ed-8b2753c8b9c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297782881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3297782881 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_key_error/latest |
| Test location | /workspace/coverage/default/12.kmac_lc_escalation.2864807445 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 120509948 ps |
| CPU time | 1.18 seconds |
| Started | May 26 02:55:43 PM PDT 24 |
| Finished | May 26 02:55:45 PM PDT 24 |
| Peak memory | 215304 kb |
| Host | smart-3a989398-5697-48a5-99ab-8d2012d1fc3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2864807445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2864807445 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/12.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/12.kmac_long_msg_and_output.1790039701 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 269597956857 ps |
| CPU time | 1617.76 seconds |
| Started | May 26 02:55:42 PM PDT 24 |
| Finished | May 26 03:22:41 PM PDT 24 |
| Peak memory | 346632 kb |
| Host | smart-283e0660-0fd3-4a55-bfd0-769dbcf55d67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790039701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a nd_output.1790039701 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/12.kmac_sideload.1700211086 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 13233054408 ps |
| CPU time | 249.78 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 02:59:50 PM PDT 24 |
| Peak memory | 243352 kb |
| Host | smart-b4467f66-06f8-4e98-a0c9-8f1d275e6b29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700211086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1700211086 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_sideload/latest |
| Test location | /workspace/coverage/default/12.kmac_smoke.165393261 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2271039308 ps |
| CPU time | 26.41 seconds |
| Started | May 26 02:55:47 PM PDT 24 |
| Finished | May 26 02:56:14 PM PDT 24 |
| Peak memory | 218000 kb |
| Host | smart-5a64edeb-07ce-4774-8c74-aaa17fc869c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165393261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.165393261 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_smoke/latest |
| Test location | /workspace/coverage/default/12.kmac_stress_all.2809964495 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 18696035347 ps |
| CPU time | 1134.37 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 03:14:33 PM PDT 24 |
| Peak memory | 371584 kb |
| Host | smart-e1b74015-7b73-4c61-8538-b168779c6f27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2809964495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2809964495 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/12.kmac_test_vectors_kmac.3158352935 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 564266507 ps |
| CPU time | 4.4 seconds |
| Started | May 26 02:55:42 PM PDT 24 |
| Finished | May 26 02:55:47 PM PDT 24 |
| Peak memory | 208676 kb |
| Host | smart-85090f67-e72c-41fd-bf58-11d97151804d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158352935 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.kmac_test_vectors_kmac.3158352935 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.2775976155 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 245471019 ps |
| CPU time | 4.8 seconds |
| Started | May 26 02:55:41 PM PDT 24 |
| Finished | May 26 02:55:47 PM PDT 24 |
| Peak memory | 215564 kb |
| Host | smart-1a3883e6-62cf-4cd7-8253-941992d65930 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775976155 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.2775976155 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/12.kmac_test_vectors_sha3_224.3549100290 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 269862043831 ps |
| CPU time | 1863.48 seconds |
| Started | May 26 02:55:48 PM PDT 24 |
| Finished | May 26 03:26:52 PM PDT 24 |
| Peak memory | 391244 kb |
| Host | smart-653ae90d-1222-4e91-afbf-740e064f2711 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3549100290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.3549100290 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/12.kmac_test_vectors_sha3_256.2142403027 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 98372752660 ps |
| CPU time | 1788.74 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 03:25:28 PM PDT 24 |
| Peak memory | 370424 kb |
| Host | smart-b4d592de-6b5c-4f0e-b8bf-71599218c2eb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2142403027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.2142403027 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/12.kmac_test_vectors_sha3_384.2392951396 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 13390578068 ps |
| CPU time | 1072.65 seconds |
| Started | May 26 02:55:52 PM PDT 24 |
| Finished | May 26 03:13:46 PM PDT 24 |
| Peak memory | 329888 kb |
| Host | smart-9ca62a6c-0eca-41d7-a7c8-d3fa13710e04 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2392951396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.2392951396 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/12.kmac_test_vectors_sha3_512.1706066948 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 47911815015 ps |
| CPU time | 963.64 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 03:11:45 PM PDT 24 |
| Peak memory | 290776 kb |
| Host | smart-6e88d846-a32c-4fae-84b9-7a76629b1907 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1706066948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.1706066948 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/12.kmac_test_vectors_shake_128.607464549 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 150359418463 ps |
| CPU time | 4200.84 seconds |
| Started | May 26 02:55:44 PM PDT 24 |
| Finished | May 26 04:05:47 PM PDT 24 |
| Peak memory | 655292 kb |
| Host | smart-78099834-abe6-43bf-a763-0d25e5b27b5d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=607464549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.607464549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/12.kmac_test_vectors_shake_256.769227741 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 982312173397 ps |
| CPU time | 4243.31 seconds |
| Started | May 26 02:55:42 PM PDT 24 |
| Finished | May 26 04:06:27 PM PDT 24 |
| Peak memory | 554296 kb |
| Host | smart-c94b45e8-aad0-4be4-9cd7-a9164fc56aa9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=769227741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.769227741 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/12.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/13.kmac_alert_test.3515946441 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 12430240 ps |
| CPU time | 0.73 seconds |
| Started | May 26 02:55:55 PM PDT 24 |
| Finished | May 26 02:55:57 PM PDT 24 |
| Peak memory | 204848 kb |
| Host | smart-b634f630-a352-4f49-a530-be57d78bd204 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515946441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3515946441 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/13.kmac_app.870611060 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 25341368980 ps |
| CPU time | 165.64 seconds |
| Started | May 26 02:55:53 PM PDT 24 |
| Finished | May 26 02:58:40 PM PDT 24 |
| Peak memory | 235692 kb |
| Host | smart-9795d11a-160f-412d-869a-fb77cfcb0b20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870611060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.870611060 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_app/latest |
| Test location | /workspace/coverage/default/13.kmac_burst_write.1155199179 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 135952237625 ps |
| CPU time | 689.39 seconds |
| Started | May 26 02:55:37 PM PDT 24 |
| Finished | May 26 03:07:08 PM PDT 24 |
| Peak memory | 229872 kb |
| Host | smart-c2738189-b272-4ce8-9ce9-d5c2dae67856 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155199179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1155199179 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/13.kmac_edn_timeout_error.2116337739 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1015633298 ps |
| CPU time | 22.88 seconds |
| Started | May 26 02:55:53 PM PDT 24 |
| Finished | May 26 02:56:17 PM PDT 24 |
| Peak memory | 223388 kb |
| Host | smart-8dc224cd-60a5-442e-8ac9-e8ff68716b93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2116337739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2116337739 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/13.kmac_entropy_mode_error.2401328633 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 973126297 ps |
| CPU time | 19.08 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 02:56:11 PM PDT 24 |
| Peak memory | 216716 kb |
| Host | smart-5d9d1bf1-1dd3-49d2-aa8e-05b2ebc9dfa9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2401328633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2401328633 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/13.kmac_entropy_refresh.326211468 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 31554280806 ps |
| CPU time | 201.11 seconds |
| Started | May 26 02:55:49 PM PDT 24 |
| Finished | May 26 02:59:12 PM PDT 24 |
| Peak memory | 237816 kb |
| Host | smart-0440b7ae-ea26-490a-a0da-c48d954738ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326211468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.326211468 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspace/13.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/13.kmac_error.3976730492 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 22916314500 ps |
| CPU time | 228.17 seconds |
| Started | May 26 02:55:52 PM PDT 24 |
| Finished | May 26 02:59:41 PM PDT 24 |
| Peak memory | 248392 kb |
| Host | smart-e4d5f4e0-c7e6-47f2-aa1e-d114f644890c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976730492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3976730492 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_error/latest |
| Test location | /workspace/coverage/default/13.kmac_key_error.3431708134 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 684638614 ps |
| CPU time | 3.68 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 02:55:55 PM PDT 24 |
| Peak memory | 215308 kb |
| Host | smart-633335ae-1c28-48ba-9f83-939c87806ea3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431708134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3431708134 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_key_error/latest |
| Test location | /workspace/coverage/default/13.kmac_lc_escalation.2912294898 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 275377449 ps |
| CPU time | 1.26 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 02:55:53 PM PDT 24 |
| Peak memory | 215312 kb |
| Host | smart-7842621f-d2c9-408b-8ad8-36b68d309ad6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912294898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2912294898 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/13.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/13.kmac_long_msg_and_output.2212789900 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 41037709301 ps |
| CPU time | 220.64 seconds |
| Started | May 26 02:55:41 PM PDT 24 |
| Finished | May 26 02:59:23 PM PDT 24 |
| Peak memory | 235800 kb |
| Host | smart-9d8830bb-8bde-4fa5-8c4a-795b43ab1b43 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212789900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a nd_output.2212789900 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/13.kmac_sideload.2366347351 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 10543382083 ps |
| CPU time | 235.64 seconds |
| Started | May 26 02:55:41 PM PDT 24 |
| Finished | May 26 02:59:38 PM PDT 24 |
| Peak memory | 238816 kb |
| Host | smart-bb2318f8-a04c-4a5e-8ad1-37b6826eff28 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366347351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2366347351 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_sideload/latest |
| Test location | /workspace/coverage/default/13.kmac_smoke.3689020696 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1691093520 ps |
| CPU time | 19.9 seconds |
| Started | May 26 02:55:39 PM PDT 24 |
| Finished | May 26 02:56:01 PM PDT 24 |
| Peak memory | 215576 kb |
| Host | smart-6b5a5e3c-72c5-4b7b-bacf-50b7a95f40bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689020696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3689020696 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_smoke/latest |
| Test location | /workspace/coverage/default/13.kmac_stress_all.2601715387 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 9077680661 ps |
| CPU time | 36.13 seconds |
| Started | May 26 02:55:49 PM PDT 24 |
| Finished | May 26 02:56:26 PM PDT 24 |
| Peak memory | 232344 kb |
| Host | smart-453e5f93-a16a-4068-8848-27e90bc808a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2601715387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2601715387 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/13.kmac_stress_all_with_rand_reset.4193238689 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 289865102888 ps |
| CPU time | 356.65 seconds |
| Started | May 26 02:55:55 PM PDT 24 |
| Finished | May 26 03:01:53 PM PDT 24 |
| Peak memory | 256908 kb |
| Host | smart-7530d7c9-bb83-4b66-ae6f-c99ec30061b6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4193238689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.4193238689 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.kmac_test_vectors_kmac.3249338217 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 182344357 ps |
| CPU time | 4.45 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 02:55:57 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-4612c064-db2e-4788-a35b-23f4fd5a37b4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249338217 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.kmac_test_vectors_kmac.3249338217 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.3886286769 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 586721944 ps |
| CPU time | 4.94 seconds |
| Started | May 26 02:55:49 PM PDT 24 |
| Finished | May 26 02:55:55 PM PDT 24 |
| Peak memory | 215500 kb |
| Host | smart-894f563b-d814-4637-b79e-be2d27d32c96 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886286769 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.3886286769 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/13.kmac_test_vectors_sha3_224.959972273 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 100231027309 ps |
| CPU time | 2200.51 seconds |
| Started | May 26 02:55:42 PM PDT 24 |
| Finished | May 26 03:32:24 PM PDT 24 |
| Peak memory | 392188 kb |
| Host | smart-652ccf45-ab1d-4f3c-9978-4ace0363e8ba |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=959972273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.959972273 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/13.kmac_test_vectors_sha3_256.3744247251 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 73668132129 ps |
| CPU time | 1563.35 seconds |
| Started | May 26 02:55:45 PM PDT 24 |
| Finished | May 26 03:21:49 PM PDT 24 |
| Peak memory | 373100 kb |
| Host | smart-71a5cb53-84a9-4874-9764-d88bd24ebc9b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3744247251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.3744247251 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/13.kmac_test_vectors_sha3_384.2985800923 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 759194937409 ps |
| CPU time | 1349.92 seconds |
| Started | May 26 02:55:44 PM PDT 24 |
| Finished | May 26 03:18:15 PM PDT 24 |
| Peak memory | 334176 kb |
| Host | smart-0e5bf68c-64e2-4a87-8a75-64d74b9dcb58 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2985800923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2985800923 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/13.kmac_test_vectors_sha3_512.971123099 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 49368474950 ps |
| CPU time | 1001.94 seconds |
| Started | May 26 02:55:42 PM PDT 24 |
| Finished | May 26 03:12:25 PM PDT 24 |
| Peak memory | 296976 kb |
| Host | smart-29445f94-8ac1-4a6b-8052-5df3f998da33 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=971123099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.971123099 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/13.kmac_test_vectors_shake_128.2734790199 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 209391068822 ps |
| CPU time | 4123.99 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 04:04:37 PM PDT 24 |
| Peak memory | 638424 kb |
| Host | smart-6c192918-9c10-470a-b0ab-212cb45c14c9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2734790199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2734790199 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/13.kmac_test_vectors_shake_256.2772317466 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 231020877979 ps |
| CPU time | 4596.71 seconds |
| Started | May 26 02:55:49 PM PDT 24 |
| Finished | May 26 04:12:27 PM PDT 24 |
| Peak memory | 571952 kb |
| Host | smart-4d1067d7-69a7-41d0-9add-eb9f1f171c48 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2772317466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2772317466 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/13.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/14.kmac_alert_test.2971822093 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 20862650 ps |
| CPU time | 0.79 seconds |
| Started | May 26 02:55:49 PM PDT 24 |
| Finished | May 26 02:55:51 PM PDT 24 |
| Peak memory | 205036 kb |
| Host | smart-bfb24fbc-ec26-4f5a-8d5f-91c4f1c52acf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971822093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2971822093 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/14.kmac_app.6393221 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 41756941584 ps |
| CPU time | 294.03 seconds |
| Started | May 26 02:55:53 PM PDT 24 |
| Finished | May 26 03:00:49 PM PDT 24 |
| Peak memory | 248476 kb |
| Host | smart-0a9333fa-8460-44ec-9be8-a527514624dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6393221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.6393221 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_app/latest |
| Test location | /workspace/coverage/default/14.kmac_burst_write.2087207694 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 59368532914 ps |
| CPU time | 380.38 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 03:02:11 PM PDT 24 |
| Peak memory | 227708 kb |
| Host | smart-d9cabd8d-a982-463e-b911-72440f826537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087207694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2087207694 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/14.kmac_edn_timeout_error.3887279876 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 2709703208 ps |
| CPU time | 14.67 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 02:56:07 PM PDT 24 |
| Peak memory | 222824 kb |
| Host | smart-c1b3d9cc-e428-4c84-880a-da27def9d24c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3887279876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3887279876 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/14.kmac_entropy_mode_error.3798308685 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 228064794 ps |
| CPU time | 14.32 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 02:56:06 PM PDT 24 |
| Peak memory | 216624 kb |
| Host | smart-3e2f98e6-fe03-4923-97d1-390c4c8927e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3798308685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3798308685 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/14.kmac_entropy_refresh.2867980032 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 8983597766 ps |
| CPU time | 203.04 seconds |
| Started | May 26 02:55:52 PM PDT 24 |
| Finished | May 26 02:59:17 PM PDT 24 |
| Peak memory | 237188 kb |
| Host | smart-9b9f4d9f-03b4-441c-a8c3-b21962780011 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867980032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2867980032 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/14.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/14.kmac_error.4261267150 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 14995630362 ps |
| CPU time | 239.65 seconds |
| Started | May 26 02:55:49 PM PDT 24 |
| Finished | May 26 02:59:50 PM PDT 24 |
| Peak memory | 256464 kb |
| Host | smart-c3b746a4-8e05-4d87-b2ca-8299b2d63948 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261267150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.4261267150 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_error/latest |
| Test location | /workspace/coverage/default/14.kmac_key_error.3990487549 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3591033463 ps |
| CPU time | 2.1 seconds |
| Started | May 26 02:55:53 PM PDT 24 |
| Finished | May 26 02:55:57 PM PDT 24 |
| Peak memory | 207204 kb |
| Host | smart-e6273c58-3478-4d67-b04e-e8484e3ef88c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990487549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3990487549 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_key_error/latest |
| Test location | /workspace/coverage/default/14.kmac_lc_escalation.3733459837 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 78876424 ps |
| CPU time | 1.3 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 02:55:53 PM PDT 24 |
| Peak memory | 216340 kb |
| Host | smart-4afe57e5-7594-49ce-b593-8cae177e74fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733459837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3733459837 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/14.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/14.kmac_long_msg_and_output.1376626615 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 25339554732 ps |
| CPU time | 896.42 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 03:10:48 PM PDT 24 |
| Peak memory | 323356 kb |
| Host | smart-79a25254-892d-42d8-819a-0e0ea2d49d19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376626615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a nd_output.1376626615 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/14.kmac_sideload.3387023344 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 766821868 ps |
| CPU time | 19.1 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 02:56:12 PM PDT 24 |
| Peak memory | 223696 kb |
| Host | smart-93f7c008-0ab7-4be8-8c74-2deb742fbcc7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387023344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3387023344 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_sideload/latest |
| Test location | /workspace/coverage/default/14.kmac_smoke.1195492973 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3508597118 ps |
| CPU time | 8.72 seconds |
| Started | May 26 02:55:49 PM PDT 24 |
| Finished | May 26 02:55:58 PM PDT 24 |
| Peak memory | 215904 kb |
| Host | smart-ceb83184-78b7-4184-bf5d-91ceee0bc3e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195492973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1195492973 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_smoke/latest |
| Test location | /workspace/coverage/default/14.kmac_stress_all.3157986700 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 17341790191 ps |
| CPU time | 1129.75 seconds |
| Started | May 26 02:55:48 PM PDT 24 |
| Finished | May 26 03:14:39 PM PDT 24 |
| Peak memory | 386612 kb |
| Host | smart-40033aaa-a2ed-4817-bc10-fb0e5c1cc712 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3157986700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3157986700 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/14.kmac_test_vectors_kmac.593596738 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 465954552 ps |
| CPU time | 4.65 seconds |
| Started | May 26 02:55:48 PM PDT 24 |
| Finished | May 26 02:55:53 PM PDT 24 |
| Peak memory | 215588 kb |
| Host | smart-62f3757a-e266-43cd-a09d-2b931188f351 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593596738 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 14.kmac_test_vectors_kmac.593596738 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.3074623494 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 139821909 ps |
| CPU time | 4 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 02:55:56 PM PDT 24 |
| Peak memory | 215748 kb |
| Host | smart-032d5bbc-4570-40ef-8145-e2c6c2fdc235 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074623494 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.3074623494 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/14.kmac_test_vectors_sha3_224.269561406 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 72433062095 ps |
| CPU time | 1434.55 seconds |
| Started | May 26 02:55:52 PM PDT 24 |
| Finished | May 26 03:19:49 PM PDT 24 |
| Peak memory | 370148 kb |
| Host | smart-cc5afdb5-72e2-4ec4-b903-f8b6ccca5273 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=269561406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.269561406 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/14.kmac_test_vectors_sha3_256.3741260515 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 162219038315 ps |
| CPU time | 1741.73 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 03:24:54 PM PDT 24 |
| Peak memory | 374776 kb |
| Host | smart-f58b1d6b-eeac-482a-9071-981b07bcfc28 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3741260515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.3741260515 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/14.kmac_test_vectors_sha3_384.2612844525 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 250224768841 ps |
| CPU time | 1339.4 seconds |
| Started | May 26 02:55:48 PM PDT 24 |
| Finished | May 26 03:18:09 PM PDT 24 |
| Peak memory | 331076 kb |
| Host | smart-ed605121-72d0-45b2-bb3b-9641aeb87c77 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2612844525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.2612844525 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/14.kmac_test_vectors_sha3_512.2622084758 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 51157356939 ps |
| CPU time | 972.18 seconds |
| Started | May 26 02:55:52 PM PDT 24 |
| Finished | May 26 03:12:06 PM PDT 24 |
| Peak memory | 292012 kb |
| Host | smart-5ce10bff-1181-4c47-95ef-debd3ac75db1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2622084758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.2622084758 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/14.kmac_test_vectors_shake_128.3788201499 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2501177423462 ps |
| CPU time | 4952.7 seconds |
| Started | May 26 02:55:55 PM PDT 24 |
| Finished | May 26 04:18:30 PM PDT 24 |
| Peak memory | 661524 kb |
| Host | smart-4c17097f-711d-491f-ba30-3cce0fbe82de |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3788201499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.3788201499 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/14.kmac_test_vectors_shake_256.1537260790 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 296011635355 ps |
| CPU time | 4518.29 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 04:11:11 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-32056f67-ff29-4688-bc9d-47411eb1c9af |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1537260790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.1537260790 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/14.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/15.kmac_alert_test.3864134185 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 29289881 ps |
| CPU time | 0.85 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 02:56:08 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-ded7c311-dc07-42ef-9a42-b9f873d754d7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864134185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3864134185 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/15.kmac_app.1049490202 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 17730457053 ps |
| CPU time | 82.44 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 02:57:30 PM PDT 24 |
| Peak memory | 227912 kb |
| Host | smart-675537e2-30ed-48e1-9519-1fbfd05874e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049490202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1049490202 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_app/latest |
| Test location | /workspace/coverage/default/15.kmac_burst_write.1844771231 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 129942037483 ps |
| CPU time | 809.2 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 03:09:22 PM PDT 24 |
| Peak memory | 231096 kb |
| Host | smart-4b505d08-5224-47f2-9f85-d59766460867 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844771231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1844771231 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/15.kmac_edn_timeout_error.3544996455 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2221966128 ps |
| CPU time | 40.59 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:56:45 PM PDT 24 |
| Peak memory | 231672 kb |
| Host | smart-329d656c-0b39-435e-b3fb-41cb6293b5c7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3544996455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3544996455 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/15.kmac_entropy_mode_error.2922415901 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1391583650 ps |
| CPU time | 35.16 seconds |
| Started | May 26 02:55:56 PM PDT 24 |
| Finished | May 26 02:56:33 PM PDT 24 |
| Peak memory | 223572 kb |
| Host | smart-20a9418f-14f1-4450-925e-4ded5d4b1cdd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2922415901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2922415901 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/15.kmac_entropy_refresh.3147663969 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 31526967477 ps |
| CPU time | 134.17 seconds |
| Started | May 26 02:56:00 PM PDT 24 |
| Finished | May 26 02:58:15 PM PDT 24 |
| Peak memory | 240012 kb |
| Host | smart-2d513d6d-ea2d-40ba-a949-be16d085951d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147663969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3147663969 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/15.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/15.kmac_error.13101098 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 58765985892 ps |
| CPU time | 387.83 seconds |
| Started | May 26 02:55:57 PM PDT 24 |
| Finished | May 26 03:02:26 PM PDT 24 |
| Peak memory | 263788 kb |
| Host | smart-fdc5fe47-852f-4ce6-b56a-f6b584f88141 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13101098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.13101098 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_error/latest |
| Test location | /workspace/coverage/default/15.kmac_key_error.15126789 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 339851356 ps |
| CPU time | 2.34 seconds |
| Started | May 26 02:55:57 PM PDT 24 |
| Finished | May 26 02:56:00 PM PDT 24 |
| Peak memory | 215256 kb |
| Host | smart-b4bae762-d527-4fae-a5e9-1d9a245dd6a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15126789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.15126789 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_key_error/latest |
| Test location | /workspace/coverage/default/15.kmac_lc_escalation.1321695284 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 76047601 ps |
| CPU time | 1.33 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:56:07 PM PDT 24 |
| Peak memory | 215296 kb |
| Host | smart-b5557cab-e7b3-43dd-ae57-9d1d9f422b1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321695284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1321695284 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/15.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/15.kmac_long_msg_and_output.1657727211 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4256907492 ps |
| CPU time | 191.06 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 02:59:04 PM PDT 24 |
| Peak memory | 236176 kb |
| Host | smart-0bbb4956-25e0-4493-852c-2045a0dc31d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657727211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a nd_output.1657727211 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/15.kmac_sideload.4039032238 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 6303499065 ps |
| CPU time | 123.02 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 02:57:56 PM PDT 24 |
| Peak memory | 229724 kb |
| Host | smart-40021c04-9b9f-47f0-abb6-cee2d44f90c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039032238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.4039032238 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_sideload/latest |
| Test location | /workspace/coverage/default/15.kmac_smoke.4214359186 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 11873570512 ps |
| CPU time | 35.52 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 02:56:28 PM PDT 24 |
| Peak memory | 218972 kb |
| Host | smart-102eb68f-ef7d-4ce3-93a4-7d603ff295d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214359186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.4214359186 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_smoke/latest |
| Test location | /workspace/coverage/default/15.kmac_stress_all.1010965471 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 30254738323 ps |
| CPU time | 922.84 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 03:11:31 PM PDT 24 |
| Peak memory | 297436 kb |
| Host | smart-28461022-a8fd-4647-bf7d-065b034b662c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1010965471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1010965471 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/15.kmac_test_vectors_kmac.1504601383 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 847606576 ps |
| CPU time | 4.79 seconds |
| Started | May 26 02:55:59 PM PDT 24 |
| Finished | May 26 02:56:05 PM PDT 24 |
| Peak memory | 215520 kb |
| Host | smart-74c0c62b-5b03-4d92-a660-0e82a4bb7aa7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504601383 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.kmac_test_vectors_kmac.1504601383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.1637351176 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 171154744 ps |
| CPU time | 4.83 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:56:10 PM PDT 24 |
| Peak memory | 215512 kb |
| Host | smart-19a7be7f-a596-4819-8f5d-3732967c63a6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637351176 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.1637351176 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/15.kmac_test_vectors_sha3_224.2529140136 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 38944027550 ps |
| CPU time | 1665.68 seconds |
| Started | May 26 02:55:50 PM PDT 24 |
| Finished | May 26 03:23:37 PM PDT 24 |
| Peak memory | 388480 kb |
| Host | smart-b74f05a3-909f-46eb-8463-67e0932ee2bb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2529140136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.2529140136 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/15.kmac_test_vectors_sha3_256.426394689 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 117361866157 ps |
| CPU time | 1487.6 seconds |
| Started | May 26 02:55:53 PM PDT 24 |
| Finished | May 26 03:20:43 PM PDT 24 |
| Peak memory | 371208 kb |
| Host | smart-70e8b656-2c25-41f4-9736-e915f71ef84b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=426394689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.426394689 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/15.kmac_test_vectors_sha3_384.976224816 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 13475166885 ps |
| CPU time | 1029.98 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 03:13:03 PM PDT 24 |
| Peak memory | 323152 kb |
| Host | smart-1e7ef567-af2d-417a-8d28-9174dfd43cb2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=976224816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.976224816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/15.kmac_test_vectors_sha3_512.2849051906 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 62126685630 ps |
| CPU time | 997.12 seconds |
| Started | May 26 02:55:49 PM PDT 24 |
| Finished | May 26 03:12:27 PM PDT 24 |
| Peak memory | 295896 kb |
| Host | smart-a5d41c4b-5985-447c-9eda-d9e0bb2fbd38 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2849051906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2849051906 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/15.kmac_test_vectors_shake_128.1350156945 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 464942355752 ps |
| CPU time | 4993.22 seconds |
| Started | May 26 02:55:51 PM PDT 24 |
| Finished | May 26 04:19:06 PM PDT 24 |
| Peak memory | 651740 kb |
| Host | smart-c437c6af-4e45-45db-a546-23042ab46cee |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1350156945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1350156945 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/15.kmac_test_vectors_shake_256.2694660580 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1031562039587 ps |
| CPU time | 3915.12 seconds |
| Started | May 26 02:55:57 PM PDT 24 |
| Finished | May 26 04:01:14 PM PDT 24 |
| Peak memory | 555256 kb |
| Host | smart-d30a9738-00d5-4bd0-bf9b-30b75746b384 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2694660580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2694660580 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/15.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/16.kmac_alert_test.3550014162 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 17142955 ps |
| CPU time | 0.74 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:56:07 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-a68a021c-93b2-4ade-a498-c9b65db3dacc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550014162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3550014162 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/16.kmac_app.1329370001 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 22848013407 ps |
| CPU time | 260.31 seconds |
| Started | May 26 02:55:59 PM PDT 24 |
| Finished | May 26 03:00:20 PM PDT 24 |
| Peak memory | 242096 kb |
| Host | smart-f6a92fdd-b828-4715-8dc1-2fd8f40def66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329370001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1329370001 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_app/latest |
| Test location | /workspace/coverage/default/16.kmac_burst_write.3813172844 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 106632454604 ps |
| CPU time | 626.35 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 03:06:34 PM PDT 24 |
| Peak memory | 230608 kb |
| Host | smart-35f2e194-fde1-40d5-833b-17ca1737a30b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813172844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3813172844 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/16.kmac_edn_timeout_error.905546742 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1043719921 ps |
| CPU time | 19.38 seconds |
| Started | May 26 02:55:57 PM PDT 24 |
| Finished | May 26 02:56:17 PM PDT 24 |
| Peak memory | 220536 kb |
| Host | smart-0b2b6d9b-deeb-460b-9476-951316ff9b61 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=905546742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.905546742 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/16.kmac_entropy_mode_error.644602606 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 5771333657 ps |
| CPU time | 18.86 seconds |
| Started | May 26 02:55:59 PM PDT 24 |
| Finished | May 26 02:56:19 PM PDT 24 |
| Peak memory | 219348 kb |
| Host | smart-b93e7dcd-b15f-4d04-8ae1-596e3839142b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=644602606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.644602606 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/16.kmac_entropy_refresh.4059961895 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 20926033449 ps |
| CPU time | 103.11 seconds |
| Started | May 26 02:55:57 PM PDT 24 |
| Finished | May 26 02:57:41 PM PDT 24 |
| Peak memory | 229656 kb |
| Host | smart-c003a065-d5fe-4ed0-b26d-59d67433eec0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059961895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.4059961895 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/16.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/16.kmac_error.1708531305 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3000053920 ps |
| CPU time | 212.32 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:59:38 PM PDT 24 |
| Peak memory | 252644 kb |
| Host | smart-ceb51fcc-d27e-4705-9b41-00d849688aeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708531305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1708531305 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_error/latest |
| Test location | /workspace/coverage/default/16.kmac_key_error.718320710 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 359371372 ps |
| CPU time | 1.76 seconds |
| Started | May 26 02:55:57 PM PDT 24 |
| Finished | May 26 02:56:00 PM PDT 24 |
| Peak memory | 207124 kb |
| Host | smart-e7157113-6dd2-48e1-af78-19675f8674fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718320710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.718320710 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_key_error/latest |
| Test location | /workspace/coverage/default/16.kmac_lc_escalation.3708617490 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 97383051 ps |
| CPU time | 1.21 seconds |
| Started | May 26 02:55:58 PM PDT 24 |
| Finished | May 26 02:56:00 PM PDT 24 |
| Peak memory | 215268 kb |
| Host | smart-2eb53511-27e9-4c83-a6fe-4ebc56dace94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708617490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3708617490 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/16.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/16.kmac_long_msg_and_output.3958930190 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 41522850568 ps |
| CPU time | 1813.52 seconds |
| Started | May 26 02:55:56 PM PDT 24 |
| Finished | May 26 03:26:11 PM PDT 24 |
| Peak memory | 428024 kb |
| Host | smart-04e97e6c-a596-4149-b7bc-c942a0ccb7f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958930190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a nd_output.3958930190 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/16.kmac_sideload.1788588900 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4708650399 ps |
| CPU time | 70.81 seconds |
| Started | May 26 02:55:55 PM PDT 24 |
| Finished | May 26 02:57:08 PM PDT 24 |
| Peak memory | 224904 kb |
| Host | smart-5fe84b8f-96a4-4528-9c3d-57eaab38b4cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788588900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1788588900 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_sideload/latest |
| Test location | /workspace/coverage/default/16.kmac_smoke.1743221724 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 11496914652 ps |
| CPU time | 50.9 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:56:56 PM PDT 24 |
| Peak memory | 219304 kb |
| Host | smart-6e4c0208-67c0-4e9c-a06d-b3ea1019db34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1743221724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1743221724 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_smoke/latest |
| Test location | /workspace/coverage/default/16.kmac_stress_all.1387895675 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 6348768992 ps |
| CPU time | 167.59 seconds |
| Started | May 26 02:55:56 PM PDT 24 |
| Finished | May 26 02:58:45 PM PDT 24 |
| Peak memory | 265104 kb |
| Host | smart-ac31cee3-d922-4158-b44e-e93c4abf1d5a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1387895675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1387895675 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/16.kmac_test_vectors_kmac.107932965 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 670920207 ps |
| CPU time | 5.01 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 02:56:13 PM PDT 24 |
| Peak memory | 215484 kb |
| Host | smart-7b54b791-fce6-45aa-9ba8-aa55e9d98316 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107932965 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 16.kmac_test_vectors_kmac.107932965 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.4220610511 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 75400847 ps |
| CPU time | 3.72 seconds |
| Started | May 26 02:56:03 PM PDT 24 |
| Finished | May 26 02:56:08 PM PDT 24 |
| Peak memory | 215528 kb |
| Host | smart-3e33a4c4-61e6-494b-a046-3f26b7035fbe |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220610511 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.4220610511 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/16.kmac_test_vectors_sha3_224.2558275157 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 78352634755 ps |
| CPU time | 1612.46 seconds |
| Started | May 26 02:55:58 PM PDT 24 |
| Finished | May 26 03:22:52 PM PDT 24 |
| Peak memory | 390656 kb |
| Host | smart-8802d2b2-9c19-4ede-88ad-c01dc1b103e0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2558275157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.2558275157 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/16.kmac_test_vectors_sha3_256.4070024371 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 494130666038 ps |
| CPU time | 1887.67 seconds |
| Started | May 26 02:55:57 PM PDT 24 |
| Finished | May 26 03:27:26 PM PDT 24 |
| Peak memory | 364316 kb |
| Host | smart-408fb02a-f20a-4727-a7b0-2eeb1ba82d1e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4070024371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.4070024371 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/16.kmac_test_vectors_sha3_384.3848920284 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 14357179261 ps |
| CPU time | 1186.54 seconds |
| Started | May 26 02:55:58 PM PDT 24 |
| Finished | May 26 03:15:46 PM PDT 24 |
| Peak memory | 337932 kb |
| Host | smart-4adf0464-8a77-4773-b37d-0728f6bb6785 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3848920284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.3848920284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/16.kmac_test_vectors_sha3_512.1430869063 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 98083911128 ps |
| CPU time | 989.31 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 03:12:35 PM PDT 24 |
| Peak memory | 291992 kb |
| Host | smart-f111bb6c-8b87-46f7-9262-8eb2af5669b2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1430869063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1430869063 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/16.kmac_test_vectors_shake_128.1100540492 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 679288748664 ps |
| CPU time | 4950 seconds |
| Started | May 26 02:55:58 PM PDT 24 |
| Finished | May 26 04:18:30 PM PDT 24 |
| Peak memory | 638040 kb |
| Host | smart-c57f10bb-56fa-4c05-9993-bd123e8cdbce |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1100540492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.1100540492 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/16.kmac_test_vectors_shake_256.228853859 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 44156935353 ps |
| CPU time | 3472.51 seconds |
| Started | May 26 02:55:58 PM PDT 24 |
| Finished | May 26 03:53:52 PM PDT 24 |
| Peak memory | 552516 kb |
| Host | smart-13b7b620-267c-49da-ba1a-f76745523d64 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=228853859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.228853859 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/16.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/17.kmac_alert_test.1040650232 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 26793315 ps |
| CPU time | 0.74 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:07 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-956bc6ad-b32a-4d05-b8b0-4e93ecbdd792 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040650232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.1040650232 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/17.kmac_app.989114691 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 29435451244 ps |
| CPU time | 142.11 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:58:29 PM PDT 24 |
| Peak memory | 232408 kb |
| Host | smart-f3b6ee82-cfdd-419d-b7c0-fd2606be6743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989114691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.989114691 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_app/latest |
| Test location | /workspace/coverage/default/17.kmac_burst_write.1252613623 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 23179200624 ps |
| CPU time | 581.83 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 03:05:47 PM PDT 24 |
| Peak memory | 230248 kb |
| Host | smart-3800ee39-e03c-49b5-9d67-fd01faa4cac3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252613623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1252613623 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/17.kmac_edn_timeout_error.1790841434 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 5644305794 ps |
| CPU time | 13.64 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:56:18 PM PDT 24 |
| Peak memory | 219364 kb |
| Host | smart-d51ea3ba-524b-46bf-8d07-0b9494e519d3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1790841434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1790841434 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/17.kmac_entropy_mode_error.1912173259 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 679987045 ps |
| CPU time | 3.84 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:10 PM PDT 24 |
| Peak memory | 216324 kb |
| Host | smart-8c5ed6bc-ecdc-4f84-a486-71a143a1f479 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1912173259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1912173259 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/17.kmac_error.1681226182 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 32380969375 ps |
| CPU time | 156.25 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 02:58:44 PM PDT 24 |
| Peak memory | 248320 kb |
| Host | smart-870730f9-8c05-4f60-93b2-448b34124d80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681226182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1681226182 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_error/latest |
| Test location | /workspace/coverage/default/17.kmac_key_error.1675800483 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1666999981 ps |
| CPU time | 3.02 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:09 PM PDT 24 |
| Peak memory | 215216 kb |
| Host | smart-c96e5ab0-b553-4ab5-b3a6-0c590bfc1a5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675800483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1675800483 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_key_error/latest |
| Test location | /workspace/coverage/default/17.kmac_lc_escalation.2146245315 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 239662291 ps |
| CPU time | 7.57 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:14 PM PDT 24 |
| Peak memory | 215552 kb |
| Host | smart-67caa086-a239-4b23-be5a-e323208150ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146245315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2146245315 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/17.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/17.kmac_long_msg_and_output.152164616 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 1342173878 ps |
| CPU time | 29.37 seconds |
| Started | May 26 02:56:00 PM PDT 24 |
| Finished | May 26 02:56:30 PM PDT 24 |
| Peak memory | 221232 kb |
| Host | smart-66d0cb70-9ff4-4a8a-acd4-999b2f5a3355 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152164616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_an d_output.152164616 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/17.kmac_sideload.3721159848 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5093906791 ps |
| CPU time | 99 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:57:44 PM PDT 24 |
| Peak memory | 227652 kb |
| Host | smart-228f64c2-3642-469b-8f16-42cbdbb8d4ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721159848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3721159848 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_sideload/latest |
| Test location | /workspace/coverage/default/17.kmac_smoke.3745460830 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2203067291 ps |
| CPU time | 43.79 seconds |
| Started | May 26 02:55:56 PM PDT 24 |
| Finished | May 26 02:56:41 PM PDT 24 |
| Peak memory | 223748 kb |
| Host | smart-2c46ec27-19ce-4aa4-b821-b8a30e35c164 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745460830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3745460830 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_smoke/latest |
| Test location | /workspace/coverage/default/17.kmac_stress_all.3703695501 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 37919347596 ps |
| CPU time | 835.95 seconds |
| Started | May 26 02:56:03 PM PDT 24 |
| Finished | May 26 03:10:00 PM PDT 24 |
| Peak memory | 348852 kb |
| Host | smart-8421a7f2-1e31-4b1f-9662-f561a9980435 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3703695501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3703695501 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/17.kmac_test_vectors_kmac.1920031776 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3343999283 ps |
| CPU time | 4.75 seconds |
| Started | May 26 02:55:57 PM PDT 24 |
| Finished | May 26 02:56:03 PM PDT 24 |
| Peak memory | 215596 kb |
| Host | smart-1b58e79b-fb07-4bf4-ab19-dd86e411b75d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920031776 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.kmac_test_vectors_kmac.1920031776 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.220378454 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 236572181 ps |
| CPU time | 3.83 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:10 PM PDT 24 |
| Peak memory | 208676 kb |
| Host | smart-c8113120-5395-47f3-836b-d6afcd062896 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220378454 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.kmac_test_vectors_kmac_xof.220378454 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/17.kmac_test_vectors_sha3_224.3759640367 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 255333930949 ps |
| CPU time | 1837.66 seconds |
| Started | May 26 02:55:58 PM PDT 24 |
| Finished | May 26 03:26:37 PM PDT 24 |
| Peak memory | 378460 kb |
| Host | smart-72209d8d-72b3-475e-bf1c-239d85e07ccb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3759640367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.3759640367 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3317113529 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 18229053720 ps |
| CPU time | 1415.68 seconds |
| Started | May 26 02:55:59 PM PDT 24 |
| Finished | May 26 03:19:36 PM PDT 24 |
| Peak memory | 369428 kb |
| Host | smart-044b7e54-1d5f-4c03-97c1-2d691588bf27 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3317113529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3317113529 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/17.kmac_test_vectors_sha3_384.561586302 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 59546378439 ps |
| CPU time | 1247.19 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 03:16:54 PM PDT 24 |
| Peak memory | 328640 kb |
| Host | smart-25456098-ff1a-484f-bab4-1023daa0bab9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=561586302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.561586302 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/17.kmac_test_vectors_sha3_512.4158993365 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 33277643042 ps |
| CPU time | 913.3 seconds |
| Started | May 26 02:55:58 PM PDT 24 |
| Finished | May 26 03:11:13 PM PDT 24 |
| Peak memory | 294848 kb |
| Host | smart-21378d3f-2a79-4ff6-93e1-687ac16c027c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4158993365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.4158993365 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/17.kmac_test_vectors_shake_128.2400290359 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 549745112604 ps |
| CPU time | 5675.52 seconds |
| Started | May 26 02:55:58 PM PDT 24 |
| Finished | May 26 04:30:35 PM PDT 24 |
| Peak memory | 656936 kb |
| Host | smart-a7a21522-d80b-4267-8241-9fad19a340d0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2400290359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.2400290359 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/17.kmac_test_vectors_shake_256.3949176747 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 295940233211 ps |
| CPU time | 3995.51 seconds |
| Started | May 26 02:56:00 PM PDT 24 |
| Finished | May 26 04:02:37 PM PDT 24 |
| Peak memory | 559408 kb |
| Host | smart-f3cb18d0-69f6-49bc-98a2-9ab5afad3eb0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3949176747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3949176747 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/17.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/18.kmac_alert_test.3884286204 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 34509250 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:56:13 PM PDT 24 |
| Finished | May 26 02:56:14 PM PDT 24 |
| Peak memory | 205036 kb |
| Host | smart-41fb189d-a68a-4ab2-9dd0-ff7bdcbe4765 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884286204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3884286204 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/18.kmac_app.1204285275 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1511567602 ps |
| CPU time | 20.51 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 02:56:26 PM PDT 24 |
| Peak memory | 223612 kb |
| Host | smart-7ae54e76-7f56-44da-a15b-b4ff8acb8e8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204285275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1204285275 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_app/latest |
| Test location | /workspace/coverage/default/18.kmac_burst_write.1385810307 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 93550996749 ps |
| CPU time | 538.82 seconds |
| Started | May 26 02:56:07 PM PDT 24 |
| Finished | May 26 03:05:08 PM PDT 24 |
| Peak memory | 229448 kb |
| Host | smart-d4d1054f-bdea-48ea-abc0-dc1d73bbca09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385810307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1385810307 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/18.kmac_edn_timeout_error.781149611 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1972896768 ps |
| CPU time | 40.59 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:47 PM PDT 24 |
| Peak memory | 223388 kb |
| Host | smart-0541751b-f074-4a8b-ae05-d2cfc5a5e075 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=781149611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.781149611 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/18.kmac_entropy_mode_error.3960354264 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 7307371028 ps |
| CPU time | 37.92 seconds |
| Started | May 26 02:56:13 PM PDT 24 |
| Finished | May 26 02:56:52 PM PDT 24 |
| Peak memory | 223452 kb |
| Host | smart-f3f76387-0f9d-4800-9cf1-2ef80269af06 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3960354264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3960354264 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/18.kmac_entropy_refresh.140579586 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 8189995878 ps |
| CPU time | 185.8 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 02:59:13 PM PDT 24 |
| Peak memory | 239848 kb |
| Host | smart-295e6ad6-5685-44d9-a9cc-6b0aedd43bf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140579586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.140579586 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspace/18.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/18.kmac_error.4238012407 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 7201539095 ps |
| CPU time | 201.8 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 02:59:30 PM PDT 24 |
| Peak memory | 248320 kb |
| Host | smart-de415137-1a6d-4dfb-92af-423027a871bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4238012407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.4238012407 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_error/latest |
| Test location | /workspace/coverage/default/18.kmac_key_error.1948054290 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4873189955 ps |
| CPU time | 6.96 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:14 PM PDT 24 |
| Peak memory | 215332 kb |
| Host | smart-f0d2d08b-c580-4eaa-b395-d44fb3fd588d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948054290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1948054290 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_key_error/latest |
| Test location | /workspace/coverage/default/18.kmac_lc_escalation.3541542694 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 60668956 ps |
| CPU time | 1.3 seconds |
| Started | May 26 02:56:14 PM PDT 24 |
| Finished | May 26 02:56:16 PM PDT 24 |
| Peak memory | 215292 kb |
| Host | smart-b4874fa7-6630-4964-a3ba-f99fca0881a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541542694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3541542694 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/18.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/18.kmac_long_msg_and_output.3548465533 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 69319318307 ps |
| CPU time | 1461.29 seconds |
| Started | May 26 02:56:08 PM PDT 24 |
| Finished | May 26 03:20:31 PM PDT 24 |
| Peak memory | 374752 kb |
| Host | smart-19d243a0-7ea2-44f3-9707-7a5ec97be36b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548465533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a nd_output.3548465533 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/18.kmac_sideload.2427445043 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 5286520715 ps |
| CPU time | 381.5 seconds |
| Started | May 26 02:56:07 PM PDT 24 |
| Finished | May 26 03:02:31 PM PDT 24 |
| Peak memory | 251868 kb |
| Host | smart-7438a2cb-df52-49b2-a9c0-91869e0cb739 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427445043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2427445043 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_sideload/latest |
| Test location | /workspace/coverage/default/18.kmac_smoke.2622153224 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 9823555364 ps |
| CPU time | 43.54 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:50 PM PDT 24 |
| Peak memory | 217392 kb |
| Host | smart-52e104bb-cd99-4170-a79b-06d8cfac12d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622153224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2622153224 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_smoke/latest |
| Test location | /workspace/coverage/default/18.kmac_stress_all.594562522 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 39564762518 ps |
| CPU time | 1201.43 seconds |
| Started | May 26 02:56:12 PM PDT 24 |
| Finished | May 26 03:16:14 PM PDT 24 |
| Peak memory | 371236 kb |
| Host | smart-b47c01cb-2119-43d0-ad1e-9371bb732702 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=594562522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.594562522 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/18.kmac_test_vectors_kmac.4161261622 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 244122615 ps |
| CPU time | 4.58 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 02:56:11 PM PDT 24 |
| Peak memory | 208636 kb |
| Host | smart-d155575c-7675-4500-8a3a-2b69262274b1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161261622 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.kmac_test_vectors_kmac.4161261622 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.108651357 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 69988664 ps |
| CPU time | 3.86 seconds |
| Started | May 26 02:56:08 PM PDT 24 |
| Finished | May 26 02:56:13 PM PDT 24 |
| Peak memory | 215532 kb |
| Host | smart-e45e6764-f43e-46d9-972a-ebd251c7e6ee |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108651357 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.kmac_test_vectors_kmac_xof.108651357 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/18.kmac_test_vectors_sha3_224.4272144062 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 73646055605 ps |
| CPU time | 1480.81 seconds |
| Started | May 26 02:56:05 PM PDT 24 |
| Finished | May 26 03:20:48 PM PDT 24 |
| Peak memory | 375888 kb |
| Host | smart-7ceb6273-15eb-4a5a-9951-4c5b0fe3fa46 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4272144062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.4272144062 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/18.kmac_test_vectors_sha3_256.3756930592 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 17491944773 ps |
| CPU time | 1389.19 seconds |
| Started | May 26 02:56:06 PM PDT 24 |
| Finished | May 26 03:19:17 PM PDT 24 |
| Peak memory | 365404 kb |
| Host | smart-22969d4a-0518-4b0a-a1ff-d339ccdc12a5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3756930592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.3756930592 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/18.kmac_test_vectors_sha3_384.4128593247 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 14100526710 ps |
| CPU time | 1108.12 seconds |
| Started | May 26 02:56:10 PM PDT 24 |
| Finished | May 26 03:14:39 PM PDT 24 |
| Peak memory | 330228 kb |
| Host | smart-de3cfaf6-74e0-40eb-aa30-805fe65fb9fb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4128593247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.4128593247 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/18.kmac_test_vectors_sha3_512.1589190458 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 34546275755 ps |
| CPU time | 850.28 seconds |
| Started | May 26 02:56:04 PM PDT 24 |
| Finished | May 26 03:10:16 PM PDT 24 |
| Peak memory | 295792 kb |
| Host | smart-ed949da6-a22b-4677-bf66-350bd248467b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1589190458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1589190458 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/18.kmac_test_vectors_shake_128.4075666527 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1078162477211 ps |
| CPU time | 5745.73 seconds |
| Started | May 26 02:56:07 PM PDT 24 |
| Finished | May 26 04:31:55 PM PDT 24 |
| Peak memory | 657772 kb |
| Host | smart-f5f19183-6986-47bf-a84b-699ebd943f7a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4075666527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.4075666527 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/18.kmac_test_vectors_shake_256.4040164359 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1446091487507 ps |
| CPU time | 4138.19 seconds |
| Started | May 26 02:56:07 PM PDT 24 |
| Finished | May 26 04:05:08 PM PDT 24 |
| Peak memory | 557008 kb |
| Host | smart-119f421c-9212-4767-b92b-51d9aa2806f8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4040164359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.4040164359 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/18.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/19.kmac_alert_test.1813270997 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 43426204 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:56:21 PM PDT 24 |
| Finished | May 26 02:56:23 PM PDT 24 |
| Peak memory | 204864 kb |
| Host | smart-0091afbf-8802-400e-b800-8048ed05731e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813270997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1813270997 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/19.kmac_app.2555446232 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 643484723 ps |
| CPU time | 12.11 seconds |
| Started | May 26 02:56:20 PM PDT 24 |
| Finished | May 26 02:56:34 PM PDT 24 |
| Peak memory | 223588 kb |
| Host | smart-17a2cfbf-cd33-4e45-9990-a605ad3bde44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555446232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2555446232 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_app/latest |
| Test location | /workspace/coverage/default/19.kmac_burst_write.1597474361 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4012221631 ps |
| CPU time | 174.17 seconds |
| Started | May 26 02:56:11 PM PDT 24 |
| Finished | May 26 02:59:06 PM PDT 24 |
| Peak memory | 224228 kb |
| Host | smart-ba4ae4b2-4342-4eed-8282-f31fb17252e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597474361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1597474361 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/19.kmac_edn_timeout_error.1125042714 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 745405189 ps |
| CPU time | 4.59 seconds |
| Started | May 26 02:56:19 PM PDT 24 |
| Finished | May 26 02:56:25 PM PDT 24 |
| Peak memory | 223448 kb |
| Host | smart-32efff2d-eb8b-451e-b5ef-6fa1edbee7f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1125042714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1125042714 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/19.kmac_entropy_mode_error.530851109 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3961838155 ps |
| CPU time | 24.04 seconds |
| Started | May 26 02:56:20 PM PDT 24 |
| Finished | May 26 02:56:45 PM PDT 24 |
| Peak memory | 223520 kb |
| Host | smart-1384725d-9e7f-4d81-b77d-f8e788006cbb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=530851109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.530851109 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/19.kmac_entropy_refresh.212014657 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 18492120414 ps |
| CPU time | 263.59 seconds |
| Started | May 26 02:56:19 PM PDT 24 |
| Finished | May 26 03:00:44 PM PDT 24 |
| Peak memory | 245592 kb |
| Host | smart-93eae22d-0307-4486-8131-58242de83ed3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=212014657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.212014657 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspace/19.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/19.kmac_error.3954114316 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 7994839359 ps |
| CPU time | 72.34 seconds |
| Started | May 26 02:56:19 PM PDT 24 |
| Finished | May 26 02:57:32 PM PDT 24 |
| Peak memory | 240044 kb |
| Host | smart-a7b48f75-85c5-4eac-a5fa-a4507d63541f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954114316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3954114316 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_error/latest |
| Test location | /workspace/coverage/default/19.kmac_key_error.1060041551 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 508021468 ps |
| CPU time | 3.68 seconds |
| Started | May 26 02:56:21 PM PDT 24 |
| Finished | May 26 02:56:26 PM PDT 24 |
| Peak memory | 207152 kb |
| Host | smart-4efc358f-70e4-4ffe-a855-c29dd56f3108 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060041551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1060041551 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_key_error/latest |
| Test location | /workspace/coverage/default/19.kmac_lc_escalation.540734043 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 231547313 ps |
| CPU time | 1.41 seconds |
| Started | May 26 02:56:23 PM PDT 24 |
| Finished | May 26 02:56:25 PM PDT 24 |
| Peak memory | 215328 kb |
| Host | smart-c3a6c67d-0e3d-4f64-b997-0842b84bd20d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540734043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.540734043 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/19.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/19.kmac_long_msg_and_output.2208576011 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 325594029846 ps |
| CPU time | 2251.85 seconds |
| Started | May 26 02:56:19 PM PDT 24 |
| Finished | May 26 03:33:52 PM PDT 24 |
| Peak memory | 443760 kb |
| Host | smart-618cf82e-ba3d-49ec-8c35-5d83077c89a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208576011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a nd_output.2208576011 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/19.kmac_sideload.2425126061 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 17050835652 ps |
| CPU time | 203.24 seconds |
| Started | May 26 02:56:14 PM PDT 24 |
| Finished | May 26 02:59:38 PM PDT 24 |
| Peak memory | 237988 kb |
| Host | smart-a3bd2b0e-c44f-4a23-a55a-0196223b07da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425126061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2425126061 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_sideload/latest |
| Test location | /workspace/coverage/default/19.kmac_smoke.2097145798 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2330678274 ps |
| CPU time | 51.19 seconds |
| Started | May 26 02:56:12 PM PDT 24 |
| Finished | May 26 02:57:04 PM PDT 24 |
| Peak memory | 221100 kb |
| Host | smart-5d8527eb-3dfe-4608-bc8b-a92ec766a83d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097145798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2097145798 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_smoke/latest |
| Test location | /workspace/coverage/default/19.kmac_stress_all.3022582165 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11115239141 ps |
| CPU time | 405.51 seconds |
| Started | May 26 02:56:20 PM PDT 24 |
| Finished | May 26 03:03:07 PM PDT 24 |
| Peak memory | 265116 kb |
| Host | smart-92f7c085-8f6f-41dc-b3f9-c2f560cc09c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3022582165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3022582165 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/19.kmac_test_vectors_kmac.4088654759 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1309618033 ps |
| CPU time | 4.36 seconds |
| Started | May 26 02:56:15 PM PDT 24 |
| Finished | May 26 02:56:20 PM PDT 24 |
| Peak memory | 215560 kb |
| Host | smart-89ce9f85-2ea6-49e5-85db-9021a05da8c5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088654759 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.4088654759 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.1596658166 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 66712465 ps |
| CPU time | 4.08 seconds |
| Started | May 26 02:56:14 PM PDT 24 |
| Finished | May 26 02:56:19 PM PDT 24 |
| Peak memory | 215548 kb |
| Host | smart-92d251d1-dba9-4239-9a4e-8b03d3724145 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596658166 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac_xof.1596658166 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/19.kmac_test_vectors_sha3_224.2952802407 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 343757434525 ps |
| CPU time | 1896.85 seconds |
| Started | May 26 02:56:15 PM PDT 24 |
| Finished | May 26 03:27:53 PM PDT 24 |
| Peak memory | 394376 kb |
| Host | smart-ab79fde5-c21f-411b-b882-32a8d4d0de38 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2952802407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.2952802407 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/19.kmac_test_vectors_sha3_256.1793475931 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 127765859059 ps |
| CPU time | 1691.25 seconds |
| Started | May 26 02:56:15 PM PDT 24 |
| Finished | May 26 03:24:27 PM PDT 24 |
| Peak memory | 375452 kb |
| Host | smart-5fc94ced-839c-4be4-81f0-dac300bba7ee |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1793475931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1793475931 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/19.kmac_test_vectors_sha3_384.3241277538 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 51330153181 ps |
| CPU time | 1340.8 seconds |
| Started | May 26 02:56:15 PM PDT 24 |
| Finished | May 26 03:18:36 PM PDT 24 |
| Peak memory | 336228 kb |
| Host | smart-e22e77a4-cd14-43bb-abb5-7174716acbb5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3241277538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3241277538 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/19.kmac_test_vectors_sha3_512.3327406864 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 100572242904 ps |
| CPU time | 1060.86 seconds |
| Started | May 26 02:56:14 PM PDT 24 |
| Finished | May 26 03:13:56 PM PDT 24 |
| Peak memory | 296532 kb |
| Host | smart-562e3367-e5b9-4b97-b16e-88666998b6cd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3327406864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3327406864 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/19.kmac_test_vectors_shake_128.1899465168 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 695466040959 ps |
| CPU time | 4966.58 seconds |
| Started | May 26 02:56:11 PM PDT 24 |
| Finished | May 26 04:18:59 PM PDT 24 |
| Peak memory | 662032 kb |
| Host | smart-0f2960eb-c544-4da3-a1fe-9b9d4edc62ea |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1899465168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.1899465168 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/19.kmac_test_vectors_shake_256.2795264186 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 43768363916 ps |
| CPU time | 3546.18 seconds |
| Started | May 26 02:56:21 PM PDT 24 |
| Finished | May 26 03:55:28 PM PDT 24 |
| Peak memory | 562588 kb |
| Host | smart-17caa6f2-75e5-4243-b232-27e2c4e9b6d2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2795264186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.2795264186 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/19.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/2.kmac_alert_test.2889811668 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 102446947 ps |
| CPU time | 0.85 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 02:55:06 PM PDT 24 |
| Peak memory | 205028 kb |
| Host | smart-1ea71262-7968-4543-bd0d-21048aa1077a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889811668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2889811668 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/2.kmac_app.1939639741 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 133431759854 ps |
| CPU time | 209.87 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:58:51 PM PDT 24 |
| Peak memory | 237268 kb |
| Host | smart-0817aba4-140b-453c-9276-4b666da2ef64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939639741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1939639741 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_app/latest |
| Test location | /workspace/coverage/default/2.kmac_app_with_partial_data.3860109724 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 14262926059 ps |
| CPU time | 250.08 seconds |
| Started | May 26 02:55:08 PM PDT 24 |
| Finished | May 26 02:59:20 PM PDT 24 |
| Peak memory | 242876 kb |
| Host | smart-8ec10e49-cad4-46d7-8f2a-6d3647f77b5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860109724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3860109724 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/2.kmac_burst_write.2405271952 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 46264981617 ps |
| CPU time | 581.61 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 03:04:42 PM PDT 24 |
| Peak memory | 230480 kb |
| Host | smart-df875629-3817-4a4d-8267-c73777a491c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405271952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2405271952 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/2.kmac_edn_timeout_error.229420887 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 460947076 ps |
| CPU time | 12.37 seconds |
| Started | May 26 02:55:02 PM PDT 24 |
| Finished | May 26 02:55:18 PM PDT 24 |
| Peak memory | 223396 kb |
| Host | smart-e3cd6168-0833-4f00-a1f1-ddd1e74557f3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=229420887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.229420887 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/2.kmac_entropy_mode_error.3282802847 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 824228339 ps |
| CPU time | 37.03 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 02:55:39 PM PDT 24 |
| Peak memory | 220604 kb |
| Host | smart-cd010edf-2c13-4f9d-a953-c938694028fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3282802847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3282802847 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/2.kmac_entropy_ready_error.1872576349 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 5831936024 ps |
| CPU time | 43.65 seconds |
| Started | May 26 02:55:04 PM PDT 24 |
| Finished | May 26 02:55:50 PM PDT 24 |
| Peak memory | 215576 kb |
| Host | smart-70a1c6ae-a005-4355-aab9-fe9542edcf71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872576349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1872576349 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/2.kmac_entropy_refresh.1615627545 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 22967285553 ps |
| CPU time | 65.59 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 02:56:10 PM PDT 24 |
| Peak memory | 224364 kb |
| Host | smart-82cd85e9-df82-4702-a467-8f8dc51e5a25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615627545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1615627545 +enable_masking=0 +s w_key_masked=0 |
| Directory | /workspace/2.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/2.kmac_key_error.1539962281 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 389941804 ps |
| CPU time | 2.59 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 02:55:10 PM PDT 24 |
| Peak memory | 207140 kb |
| Host | smart-a2cd1eeb-c2b0-4df5-a5ec-7064a5f90b91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539962281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1539962281 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_key_error/latest |
| Test location | /workspace/coverage/default/2.kmac_lc_escalation.94524298 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 1351605132 ps |
| CPU time | 11.92 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 02:55:14 PM PDT 24 |
| Peak memory | 223668 kb |
| Host | smart-41a303d5-a714-48e1-95bd-5af28a05b180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94524298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.94524298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/2.kmac_long_msg_and_output.1892353536 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 852764797787 ps |
| CPU time | 1802.83 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 03:25:05 PM PDT 24 |
| Peak memory | 398420 kb |
| Host | smart-b77d25bd-f7ba-42f2-a9dc-b6a19dc0b5e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892353536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an d_output.1892353536 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/2.kmac_mubi.1432113246 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 8358711118 ps |
| CPU time | 49.55 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 02:55:57 PM PDT 24 |
| Peak memory | 224440 kb |
| Host | smart-cc62f449-8354-49ce-a8c6-72cd541f250c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432113246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1432113246 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_mubi/latest |
| Test location | /workspace/coverage/default/2.kmac_sec_cm.3056737721 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 5883091607 ps |
| CPU time | 23.38 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:55:41 PM PDT 24 |
| Peak memory | 242512 kb |
| Host | smart-82d600ac-7637-4e5f-8661-922e1740a988 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056737721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3056737721 +enable_maski ng=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_sec_cm/latest |
| Test location | /workspace/coverage/default/2.kmac_sideload.897244057 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 7771545769 ps |
| CPU time | 289.78 seconds |
| Started | May 26 02:55:04 PM PDT 24 |
| Finished | May 26 02:59:56 PM PDT 24 |
| Peak memory | 243640 kb |
| Host | smart-538f0fcc-03fd-447e-b84b-0273904013c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897244057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.897244057 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_sideload/latest |
| Test location | /workspace/coverage/default/2.kmac_smoke.3693958785 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2374712697 ps |
| CPU time | 6.73 seconds |
| Started | May 26 02:55:02 PM PDT 24 |
| Finished | May 26 02:55:12 PM PDT 24 |
| Peak memory | 215696 kb |
| Host | smart-a9fd6d80-ad5a-4740-9928-c44acc3c37e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693958785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3693958785 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_smoke/latest |
| Test location | /workspace/coverage/default/2.kmac_stress_all.2489686097 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 32038930661 ps |
| CPU time | 175.57 seconds |
| Started | May 26 02:55:03 PM PDT 24 |
| Finished | May 26 02:58:02 PM PDT 24 |
| Peak memory | 245636 kb |
| Host | smart-62a0a40b-64d7-41cf-9e75-fbe6b19b5b7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2489686097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2489686097 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/2.kmac_stress_all_with_rand_reset.3044098289 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 34718153741 ps |
| CPU time | 1720.31 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 03:23:45 PM PDT 24 |
| Peak memory | 409288 kb |
| Host | smart-4993ce50-d2c4-4dfd-9f74-6a1728fdb0a2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3044098289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.3044098289 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.kmac_test_vectors_kmac.4259550580 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 415056033 ps |
| CPU time | 4.17 seconds |
| Started | May 26 02:55:04 PM PDT 24 |
| Finished | May 26 02:55:11 PM PDT 24 |
| Peak memory | 215564 kb |
| Host | smart-48662cb4-ae8c-42bf-85d4-081dcdcc3a61 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259550580 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.kmac_test_vectors_kmac.4259550580 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.1868180612 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 65125895 ps |
| CPU time | 3.83 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 02:55:11 PM PDT 24 |
| Peak memory | 215504 kb |
| Host | smart-13c84e50-c01b-4d35-8f2e-49ce61b70d18 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868180612 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1868180612 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/2.kmac_test_vectors_sha3_224.1115617740 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 181164863126 ps |
| CPU time | 1859.94 seconds |
| Started | May 26 02:55:02 PM PDT 24 |
| Finished | May 26 03:26:06 PM PDT 24 |
| Peak memory | 404124 kb |
| Host | smart-84e956f4-5930-45b2-b342-5f78d935c6e5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1115617740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1115617740 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/2.kmac_test_vectors_sha3_256.2101561981 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 377002077816 ps |
| CPU time | 1814.22 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 03:25:22 PM PDT 24 |
| Peak memory | 370144 kb |
| Host | smart-fd7a8322-2ebc-4523-a076-12743d3f85b6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2101561981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2101561981 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/2.kmac_test_vectors_sha3_384.2417812408 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 273240494238 ps |
| CPU time | 1336.72 seconds |
| Started | May 26 02:55:02 PM PDT 24 |
| Finished | May 26 03:17:22 PM PDT 24 |
| Peak memory | 330772 kb |
| Host | smart-b4a8f0ea-84d1-4fd4-bd7e-bc4f43b09418 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2417812408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2417812408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/2.kmac_test_vectors_sha3_512.3540048062 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 9791375205 ps |
| CPU time | 783.94 seconds |
| Started | May 26 02:55:02 PM PDT 24 |
| Finished | May 26 03:08:09 PM PDT 24 |
| Peak memory | 292940 kb |
| Host | smart-b8417036-cdc7-4a9d-94cf-23102d6c401a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3540048062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3540048062 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/2.kmac_test_vectors_shake_128.3309226038 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 173014358329 ps |
| CPU time | 5214.37 seconds |
| Started | May 26 02:55:07 PM PDT 24 |
| Finished | May 26 04:22:04 PM PDT 24 |
| Peak memory | 655500 kb |
| Host | smart-8d483198-edca-4e83-a283-32bb0a34736f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3309226038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3309226038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/20.kmac_alert_test.3378808340 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 19782297 ps |
| CPU time | 0.78 seconds |
| Started | May 26 02:56:27 PM PDT 24 |
| Finished | May 26 02:56:29 PM PDT 24 |
| Peak memory | 205036 kb |
| Host | smart-1263f918-b3ba-4812-a21f-165b29f884f4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378808340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3378808340 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/20.kmac_app.2147409319 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1695899520 ps |
| CPU time | 16.33 seconds |
| Started | May 26 02:56:27 PM PDT 24 |
| Finished | May 26 02:56:45 PM PDT 24 |
| Peak memory | 216504 kb |
| Host | smart-c143e9ce-44f8-455c-9228-8dc2f17cbd7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147409319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2147409319 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_app/latest |
| Test location | /workspace/coverage/default/20.kmac_burst_write.2129987223 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 9675399437 ps |
| CPU time | 57.61 seconds |
| Started | May 26 02:56:19 PM PDT 24 |
| Finished | May 26 02:57:18 PM PDT 24 |
| Peak memory | 219912 kb |
| Host | smart-d50cf2b3-28c9-40c8-9ad3-5e4dfda7c3ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129987223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2129987223 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/20.kmac_entropy_refresh.3770354819 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10709397711 ps |
| CPU time | 120.1 seconds |
| Started | May 26 02:56:26 PM PDT 24 |
| Finished | May 26 02:58:28 PM PDT 24 |
| Peak memory | 232084 kb |
| Host | smart-ceabda3d-a663-4ba5-8741-40adde86ca7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770354819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3770354819 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/20.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/20.kmac_error.1996165903 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 3294332216 ps |
| CPU time | 114.7 seconds |
| Started | May 26 02:56:26 PM PDT 24 |
| Finished | May 26 02:58:22 PM PDT 24 |
| Peak memory | 248404 kb |
| Host | smart-1cdfe058-b457-4897-b9dc-cc5b1f3d5838 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1996165903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1996165903 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_error/latest |
| Test location | /workspace/coverage/default/20.kmac_key_error.3416527465 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2309808382 ps |
| CPU time | 4.36 seconds |
| Started | May 26 02:56:26 PM PDT 24 |
| Finished | May 26 02:56:31 PM PDT 24 |
| Peak memory | 215380 kb |
| Host | smart-95d6bc1a-f5a7-4d25-9006-3354b692c402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416527465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3416527465 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_key_error/latest |
| Test location | /workspace/coverage/default/20.kmac_lc_escalation.1979658882 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 29115128 ps |
| CPU time | 1.26 seconds |
| Started | May 26 02:56:27 PM PDT 24 |
| Finished | May 26 02:56:29 PM PDT 24 |
| Peak memory | 215372 kb |
| Host | smart-34434733-6152-4619-afe8-55428d425f10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979658882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1979658882 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/20.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/20.kmac_long_msg_and_output.3544987698 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1186450821 ps |
| CPU time | 27.4 seconds |
| Started | May 26 02:56:27 PM PDT 24 |
| Finished | May 26 02:56:55 PM PDT 24 |
| Peak memory | 219808 kb |
| Host | smart-c960832c-809a-499b-8a74-fd472d971f93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544987698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a nd_output.3544987698 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/20.kmac_sideload.967508686 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 332834512 ps |
| CPU time | 9.23 seconds |
| Started | May 26 02:56:27 PM PDT 24 |
| Finished | May 26 02:56:37 PM PDT 24 |
| Peak memory | 220028 kb |
| Host | smart-6ab277ff-b9a8-4eaf-8311-b7a698afaec1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967508686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.967508686 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_sideload/latest |
| Test location | /workspace/coverage/default/20.kmac_smoke.114627141 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2402976178 ps |
| CPU time | 51.65 seconds |
| Started | May 26 02:56:18 PM PDT 24 |
| Finished | May 26 02:57:11 PM PDT 24 |
| Peak memory | 221516 kb |
| Host | smart-2917afed-1ce3-4aa8-b19a-0d025a46329d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114627141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.114627141 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_smoke/latest |
| Test location | /workspace/coverage/default/20.kmac_stress_all.2547168419 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 259548676715 ps |
| CPU time | 1366.7 seconds |
| Started | May 26 02:56:28 PM PDT 24 |
| Finished | May 26 03:19:16 PM PDT 24 |
| Peak memory | 367428 kb |
| Host | smart-aa254ed6-cc6f-4655-99f5-6eb779c6c9e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2547168419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2547168419 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/20.kmac_stress_all_with_rand_reset.780588551 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 55430752813 ps |
| CPU time | 318.4 seconds |
| Started | May 26 02:56:29 PM PDT 24 |
| Finished | May 26 03:01:48 PM PDT 24 |
| Peak memory | 255848 kb |
| Host | smart-9eac6e83-ccb3-4117-9970-450c2f735054 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=780588551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all_with_rand_reset.780588551 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.kmac_test_vectors_kmac.2896134505 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 63331254 ps |
| CPU time | 3.87 seconds |
| Started | May 26 02:56:28 PM PDT 24 |
| Finished | May 26 02:56:33 PM PDT 24 |
| Peak memory | 215540 kb |
| Host | smart-451e4fa6-bde8-4131-8183-d90ad3361f61 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896134505 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.kmac_test_vectors_kmac.2896134505 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.3258686651 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 326749065 ps |
| CPU time | 4.34 seconds |
| Started | May 26 02:56:29 PM PDT 24 |
| Finished | May 26 02:56:35 PM PDT 24 |
| Peak memory | 215528 kb |
| Host | smart-decc2b41-67d9-45a2-94fb-cd0d0da6fc7f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258686651 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.3258686651 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/20.kmac_test_vectors_sha3_224.3814486979 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 38782803098 ps |
| CPU time | 1544.94 seconds |
| Started | May 26 02:56:19 PM PDT 24 |
| Finished | May 26 03:22:06 PM PDT 24 |
| Peak memory | 387560 kb |
| Host | smart-adf893e1-4443-4793-b1d1-8e65508a8943 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3814486979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3814486979 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/20.kmac_test_vectors_sha3_256.1005348738 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 252445674920 ps |
| CPU time | 1831.39 seconds |
| Started | May 26 02:56:19 PM PDT 24 |
| Finished | May 26 03:26:51 PM PDT 24 |
| Peak memory | 371272 kb |
| Host | smart-1ef1825c-fa72-4fd8-976c-c998d5a74e71 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1005348738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.1005348738 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/20.kmac_test_vectors_sha3_384.1819800134 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 58226689487 ps |
| CPU time | 1233.2 seconds |
| Started | May 26 02:56:20 PM PDT 24 |
| Finished | May 26 03:16:55 PM PDT 24 |
| Peak memory | 340960 kb |
| Host | smart-c4c277a9-8417-45b4-809e-79fd46d5b887 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1819800134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.1819800134 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/20.kmac_test_vectors_sha3_512.467388614 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 9271074255 ps |
| CPU time | 694.05 seconds |
| Started | May 26 02:56:27 PM PDT 24 |
| Finished | May 26 03:08:02 PM PDT 24 |
| Peak memory | 288080 kb |
| Host | smart-9d2e4244-6abf-4718-9b11-491371738b66 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=467388614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.467388614 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/20.kmac_test_vectors_shake_128.846769205 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 261977273681 ps |
| CPU time | 5234.98 seconds |
| Started | May 26 02:56:21 PM PDT 24 |
| Finished | May 26 04:23:38 PM PDT 24 |
| Peak memory | 640828 kb |
| Host | smart-37a24e07-cc3a-4351-8f42-27cd02d9434e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=846769205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.846769205 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/20.kmac_test_vectors_shake_256.3550808967 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 533739463376 ps |
| CPU time | 4218.49 seconds |
| Started | May 26 02:56:26 PM PDT 24 |
| Finished | May 26 04:06:46 PM PDT 24 |
| Peak memory | 554268 kb |
| Host | smart-4d83c00c-831c-4069-a49d-3b25e3468c8e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3550808967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3550808967 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/20.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/21.kmac_alert_test.3916284079 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 13651925 ps |
| CPU time | 0.78 seconds |
| Started | May 26 02:56:34 PM PDT 24 |
| Finished | May 26 02:56:36 PM PDT 24 |
| Peak memory | 204900 kb |
| Host | smart-409a6ff3-8799-4a2b-9a13-e657273aae65 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916284079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3916284079 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/21.kmac_app.1469911377 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2004132136 ps |
| CPU time | 89.88 seconds |
| Started | May 26 02:56:28 PM PDT 24 |
| Finished | May 26 02:57:59 PM PDT 24 |
| Peak memory | 228516 kb |
| Host | smart-fc399e6a-8611-4c78-a672-a9970e3bc66f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469911377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1469911377 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_app/latest |
| Test location | /workspace/coverage/default/21.kmac_burst_write.2206398334 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 21638634820 ps |
| CPU time | 695.26 seconds |
| Started | May 26 02:56:28 PM PDT 24 |
| Finished | May 26 03:08:04 PM PDT 24 |
| Peak memory | 230960 kb |
| Host | smart-ef4b4eab-3802-4e03-a237-787e1a5ff134 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206398334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.2206398334 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/21.kmac_entropy_refresh.1238115747 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 5289203746 ps |
| CPU time | 81.7 seconds |
| Started | May 26 02:56:29 PM PDT 24 |
| Finished | May 26 02:57:51 PM PDT 24 |
| Peak memory | 228464 kb |
| Host | smart-ec8c9894-fab8-4490-a178-56708295f5c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238115747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1238115747 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/21.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/21.kmac_error.2687051062 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 1532439653 ps |
| CPU time | 121.53 seconds |
| Started | May 26 02:56:33 PM PDT 24 |
| Finished | May 26 02:58:35 PM PDT 24 |
| Peak memory | 240028 kb |
| Host | smart-0188af97-e3a3-4b40-9737-dfb4588a43e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687051062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2687051062 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_error/latest |
| Test location | /workspace/coverage/default/21.kmac_key_error.3855200809 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 152826407 ps |
| CPU time | 1.43 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 02:56:37 PM PDT 24 |
| Peak memory | 206956 kb |
| Host | smart-34fb3a2b-a8b8-4016-9108-32cf44612819 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855200809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3855200809 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_key_error/latest |
| Test location | /workspace/coverage/default/21.kmac_lc_escalation.4268274869 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 35750106 ps |
| CPU time | 1.25 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 02:56:37 PM PDT 24 |
| Peak memory | 215376 kb |
| Host | smart-3b595167-522b-4d01-89bc-ed792ee1d7ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268274869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.4268274869 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/21.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/21.kmac_long_msg_and_output.2904795529 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 22220059069 ps |
| CPU time | 1785.76 seconds |
| Started | May 26 02:56:26 PM PDT 24 |
| Finished | May 26 03:26:12 PM PDT 24 |
| Peak memory | 425868 kb |
| Host | smart-9f7c706a-bb25-4f13-a8bd-57a75f5c9eeb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904795529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a nd_output.2904795529 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/21.kmac_sideload.3241604813 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 67866746 ps |
| CPU time | 5.03 seconds |
| Started | May 26 02:56:29 PM PDT 24 |
| Finished | May 26 02:56:35 PM PDT 24 |
| Peak memory | 219636 kb |
| Host | smart-06c08538-cdf6-469c-8ef7-8f00c602f5cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241604813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3241604813 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_sideload/latest |
| Test location | /workspace/coverage/default/21.kmac_smoke.3241908413 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1747071793 ps |
| CPU time | 23.5 seconds |
| Started | May 26 02:56:28 PM PDT 24 |
| Finished | May 26 02:56:53 PM PDT 24 |
| Peak memory | 223684 kb |
| Host | smart-43855d63-d4f2-4931-985e-7ec4c2635b2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241908413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3241908413 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_smoke/latest |
| Test location | /workspace/coverage/default/21.kmac_stress_all.738839192 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 3069973262 ps |
| CPU time | 50.99 seconds |
| Started | May 26 02:56:34 PM PDT 24 |
| Finished | May 26 02:57:26 PM PDT 24 |
| Peak memory | 223912 kb |
| Host | smart-b39b9cf1-82dc-4b91-bdee-351a262dd9c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=738839192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.738839192 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/21.kmac_stress_all_with_rand_reset.3413380208 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 131100674991 ps |
| CPU time | 577.59 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 03:06:14 PM PDT 24 |
| Peak memory | 265128 kb |
| Host | smart-77cac94d-6e07-43f9-ab2c-5e2b87f913da |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3413380208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.3413380208 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.kmac_test_vectors_kmac.2034035802 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 195033236 ps |
| CPU time | 4.21 seconds |
| Started | May 26 02:56:28 PM PDT 24 |
| Finished | May 26 02:56:33 PM PDT 24 |
| Peak memory | 215596 kb |
| Host | smart-6ff3963f-70c3-4f8b-85e9-16494037d809 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034035802 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.kmac_test_vectors_kmac.2034035802 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.3791456104 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 247748564 ps |
| CPU time | 4.9 seconds |
| Started | May 26 02:56:26 PM PDT 24 |
| Finished | May 26 02:56:31 PM PDT 24 |
| Peak memory | 215528 kb |
| Host | smart-29873e1a-f6a2-4399-a5ee-30543567a63c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791456104 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac_xof.3791456104 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/21.kmac_test_vectors_sha3_224.1778883955 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 18577268641 ps |
| CPU time | 1547.74 seconds |
| Started | May 26 02:56:27 PM PDT 24 |
| Finished | May 26 03:22:17 PM PDT 24 |
| Peak memory | 386856 kb |
| Host | smart-e7217cb4-b6c0-41b1-834b-e9558ba32013 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1778883955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1778883955 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2040950164 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 23351081045 ps |
| CPU time | 1437.2 seconds |
| Started | May 26 02:56:28 PM PDT 24 |
| Finished | May 26 03:20:26 PM PDT 24 |
| Peak memory | 369600 kb |
| Host | smart-00dfc17e-83e8-4926-87b5-7bcf6c223fe4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2040950164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2040950164 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/21.kmac_test_vectors_sha3_384.1451778960 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 660622809628 ps |
| CPU time | 1335.65 seconds |
| Started | May 26 02:56:27 PM PDT 24 |
| Finished | May 26 03:18:44 PM PDT 24 |
| Peak memory | 327608 kb |
| Host | smart-ccacc7ae-120e-489b-85ca-c6a147cf8e07 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1451778960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.1451778960 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/21.kmac_test_vectors_sha3_512.2127227530 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 34841886255 ps |
| CPU time | 1000.41 seconds |
| Started | May 26 02:56:25 PM PDT 24 |
| Finished | May 26 03:13:07 PM PDT 24 |
| Peak memory | 301652 kb |
| Host | smart-a879e349-4013-4d11-91c8-3de418e57de1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2127227530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2127227530 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/21.kmac_test_vectors_shake_128.442963142 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1502402023036 ps |
| CPU time | 5083.81 seconds |
| Started | May 26 02:56:29 PM PDT 24 |
| Finished | May 26 04:21:14 PM PDT 24 |
| Peak memory | 661736 kb |
| Host | smart-640245a1-082a-436f-9f00-3c033e98a75d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=442963142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.442963142 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/21.kmac_test_vectors_shake_256.689581525 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 556112239362 ps |
| CPU time | 4296.76 seconds |
| Started | May 26 02:56:29 PM PDT 24 |
| Finished | May 26 04:08:07 PM PDT 24 |
| Peak memory | 556924 kb |
| Host | smart-f218cca7-3d15-47c0-8fa5-e5eb384f69f7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=689581525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.689581525 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/21.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/22.kmac_alert_test.4292528160 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 12098002 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:56:34 PM PDT 24 |
| Finished | May 26 02:56:36 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-a818e69a-7777-42f6-bdca-21fe98d6f4bd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292528160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.4292528160 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/22.kmac_app.421281463 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4616812748 ps |
| CPU time | 199.88 seconds |
| Started | May 26 02:56:33 PM PDT 24 |
| Finished | May 26 02:59:54 PM PDT 24 |
| Peak memory | 241052 kb |
| Host | smart-e9a6858f-2e80-481d-8f9b-f9e9b2d968ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421281463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.421281463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_app/latest |
| Test location | /workspace/coverage/default/22.kmac_burst_write.4117643906 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 1531190798 ps |
| CPU time | 46.89 seconds |
| Started | May 26 02:56:36 PM PDT 24 |
| Finished | May 26 02:57:24 PM PDT 24 |
| Peak memory | 223704 kb |
| Host | smart-d6c13ade-55f6-46df-a29e-5dbb7f5b3403 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117643906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.4117643906 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/22.kmac_entropy_refresh.3507531102 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 52646091503 ps |
| CPU time | 338.14 seconds |
| Started | May 26 02:56:34 PM PDT 24 |
| Finished | May 26 03:02:14 PM PDT 24 |
| Peak memory | 247228 kb |
| Host | smart-d51e34aa-cd57-4c12-bec5-cc62ec84a9de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507531102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3507531102 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/22.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/22.kmac_error.1774623378 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 10820554603 ps |
| CPU time | 64.05 seconds |
| Started | May 26 02:56:33 PM PDT 24 |
| Finished | May 26 02:57:38 PM PDT 24 |
| Peak memory | 232204 kb |
| Host | smart-7210e5e9-c9f2-40d9-9665-b0d2c59f613e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774623378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1774623378 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_error/latest |
| Test location | /workspace/coverage/default/22.kmac_key_error.1672045593 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 2756910110 ps |
| CPU time | 3.76 seconds |
| Started | May 26 02:56:34 PM PDT 24 |
| Finished | May 26 02:56:39 PM PDT 24 |
| Peak memory | 207140 kb |
| Host | smart-acbd87a8-0cdd-4302-bcc3-ebb5f13b4328 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672045593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1672045593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_key_error/latest |
| Test location | /workspace/coverage/default/22.kmac_lc_escalation.532466351 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 52489637 ps |
| CPU time | 1.31 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 02:56:38 PM PDT 24 |
| Peak memory | 215220 kb |
| Host | smart-736880f5-20b5-4308-ae5e-f34e6d3264fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532466351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.532466351 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/22.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/22.kmac_long_msg_and_output.493685203 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 363346141619 ps |
| CPU time | 2124.03 seconds |
| Started | May 26 02:56:34 PM PDT 24 |
| Finished | May 26 03:32:00 PM PDT 24 |
| Peak memory | 397072 kb |
| Host | smart-68a3a821-0ada-498a-a5c6-43241fc7fc81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493685203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_an d_output.493685203 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/22.kmac_sideload.1216455734 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1884470049 ps |
| CPU time | 48.61 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 02:57:24 PM PDT 24 |
| Peak memory | 229144 kb |
| Host | smart-36e952e6-4747-440b-9f65-1ae32cfef18e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216455734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1216455734 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_sideload/latest |
| Test location | /workspace/coverage/default/22.kmac_smoke.1380114625 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 2016005442 ps |
| CPU time | 40.2 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 02:57:16 PM PDT 24 |
| Peak memory | 218944 kb |
| Host | smart-8b83c892-3d11-4107-9a59-bdbf9cfb4e35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380114625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1380114625 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_smoke/latest |
| Test location | /workspace/coverage/default/22.kmac_stress_all.1733352591 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 13113039837 ps |
| CPU time | 890.24 seconds |
| Started | May 26 02:56:34 PM PDT 24 |
| Finished | May 26 03:11:25 PM PDT 24 |
| Peak memory | 354884 kb |
| Host | smart-82b9eae2-3ad6-477b-ab8e-d0d219928c85 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1733352591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1733352591 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/22.kmac_test_vectors_kmac.3513882 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 75820542 ps |
| CPU time | 4.47 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 02:56:40 PM PDT 24 |
| Peak memory | 215596 kb |
| Host | smart-9a621184-7b81-4c4c-8fd4-8cf20f7525a3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513882 -assert nopostproc +UVM_TESTNAME=kmac_base_te st +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.kmac_test_vectors_kmac.3513882 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.320677812 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 705480053 ps |
| CPU time | 4.76 seconds |
| Started | May 26 02:56:36 PM PDT 24 |
| Finished | May 26 02:56:41 PM PDT 24 |
| Peak memory | 215536 kb |
| Host | smart-0ad6250c-0561-4aa7-b89e-d64b3bb098af |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320677812 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 22.kmac_test_vectors_kmac_xof.320677812 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/22.kmac_test_vectors_sha3_224.2256868257 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 275166083679 ps |
| CPU time | 1884.23 seconds |
| Started | May 26 02:56:34 PM PDT 24 |
| Finished | May 26 03:28:00 PM PDT 24 |
| Peak memory | 398056 kb |
| Host | smart-ff8c6635-53a9-4734-aa89-cd71c4f960c3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2256868257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.2256868257 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/22.kmac_test_vectors_sha3_256.2647747739 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 127990762176 ps |
| CPU time | 1782.14 seconds |
| Started | May 26 02:56:33 PM PDT 24 |
| Finished | May 26 03:26:17 PM PDT 24 |
| Peak memory | 375780 kb |
| Host | smart-dda4e565-9eea-4252-9039-986e39697f69 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2647747739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.2647747739 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/22.kmac_test_vectors_sha3_384.4161539388 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 13805593336 ps |
| CPU time | 1050.29 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 03:14:06 PM PDT 24 |
| Peak memory | 329184 kb |
| Host | smart-4651c63c-eb3c-4651-9631-be791783904b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4161539388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.4161539388 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/22.kmac_test_vectors_sha3_512.3673946033 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 18418674372 ps |
| CPU time | 734.09 seconds |
| Started | May 26 02:56:35 PM PDT 24 |
| Finished | May 26 03:08:50 PM PDT 24 |
| Peak memory | 296356 kb |
| Host | smart-5ecdfffc-b6d0-4d7e-b2d2-f65e0b40dc55 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3673946033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.3673946033 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/22.kmac_test_vectors_shake_128.3724008692 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 203104789613 ps |
| CPU time | 4353.5 seconds |
| Started | May 26 02:56:33 PM PDT 24 |
| Finished | May 26 04:09:08 PM PDT 24 |
| Peak memory | 648524 kb |
| Host | smart-00d63860-949a-40f3-ae4a-7423cd333c60 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3724008692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.3724008692 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/22.kmac_test_vectors_shake_256.2142999257 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 893691892574 ps |
| CPU time | 4522.52 seconds |
| Started | May 26 02:56:33 PM PDT 24 |
| Finished | May 26 04:11:58 PM PDT 24 |
| Peak memory | 552744 kb |
| Host | smart-850ede10-b280-40ff-9843-ef8a83ccf877 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2142999257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.2142999257 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/22.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/23.kmac_alert_test.2194610795 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 52629830 ps |
| CPU time | 0.8 seconds |
| Started | May 26 02:56:51 PM PDT 24 |
| Finished | May 26 02:56:53 PM PDT 24 |
| Peak memory | 204828 kb |
| Host | smart-ca98ddd3-c529-4cc2-8306-576e19250372 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194610795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2194610795 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/23.kmac_app.3251243309 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1793782584 ps |
| CPU time | 46.01 seconds |
| Started | May 26 02:56:43 PM PDT 24 |
| Finished | May 26 02:57:30 PM PDT 24 |
| Peak memory | 223728 kb |
| Host | smart-ea44e41a-b212-44a9-bd73-6db8a8a8d526 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251243309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3251243309 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_app/latest |
| Test location | /workspace/coverage/default/23.kmac_burst_write.2701439970 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 166392398599 ps |
| CPU time | 790.01 seconds |
| Started | May 26 02:56:41 PM PDT 24 |
| Finished | May 26 03:09:53 PM PDT 24 |
| Peak memory | 230520 kb |
| Host | smart-8a6b1e74-9c6f-47a4-9497-153e4b280fa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701439970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2701439970 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/23.kmac_entropy_refresh.4011362082 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 5651392495 ps |
| CPU time | 229.05 seconds |
| Started | May 26 02:56:42 PM PDT 24 |
| Finished | May 26 03:00:33 PM PDT 24 |
| Peak memory | 243748 kb |
| Host | smart-2a38279e-c2b6-4a77-b36a-54717e0bba34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011362082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.4011362082 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/23.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/23.kmac_error.909440212 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1865787121 ps |
| CPU time | 66.95 seconds |
| Started | May 26 02:56:42 PM PDT 24 |
| Finished | May 26 02:57:51 PM PDT 24 |
| Peak memory | 240032 kb |
| Host | smart-d71cb6f5-7d66-4765-b7da-35bccddaa3e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909440212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.909440212 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_error/latest |
| Test location | /workspace/coverage/default/23.kmac_key_error.3481445584 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 5198937869 ps |
| CPU time | 5.84 seconds |
| Started | May 26 02:56:42 PM PDT 24 |
| Finished | May 26 02:56:49 PM PDT 24 |
| Peak memory | 215352 kb |
| Host | smart-f0f52269-a0a9-4fdf-a5c4-895919b6cf3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481445584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.3481445584 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_key_error/latest |
| Test location | /workspace/coverage/default/23.kmac_lc_escalation.3027317808 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 125740745 ps |
| CPU time | 1.41 seconds |
| Started | May 26 02:56:43 PM PDT 24 |
| Finished | May 26 02:56:45 PM PDT 24 |
| Peak memory | 215300 kb |
| Host | smart-c788efa0-2d1f-4897-8661-6112cbb3e605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027317808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3027317808 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/23.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/23.kmac_long_msg_and_output.609300028 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 55931327123 ps |
| CPU time | 1238.85 seconds |
| Started | May 26 02:56:44 PM PDT 24 |
| Finished | May 26 03:17:24 PM PDT 24 |
| Peak memory | 337736 kb |
| Host | smart-20b65ed2-ab78-4cf7-a1b7-13738c8bdb00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609300028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_an d_output.609300028 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/23.kmac_sideload.777820720 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4209869851 ps |
| CPU time | 108.05 seconds |
| Started | May 26 02:56:41 PM PDT 24 |
| Finished | May 26 02:58:31 PM PDT 24 |
| Peak memory | 228356 kb |
| Host | smart-5de214b3-64ee-49f1-b58a-0c8ff9055a22 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777820720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.777820720 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_sideload/latest |
| Test location | /workspace/coverage/default/23.kmac_smoke.1680785942 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 13414830340 ps |
| CPU time | 57.22 seconds |
| Started | May 26 02:56:33 PM PDT 24 |
| Finished | May 26 02:57:32 PM PDT 24 |
| Peak memory | 223760 kb |
| Host | smart-7ffae990-744e-4ff4-abdb-0b6ff1b26ebd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680785942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1680785942 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_smoke/latest |
| Test location | /workspace/coverage/default/23.kmac_stress_all.38648481 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 39384234754 ps |
| CPU time | 229.03 seconds |
| Started | May 26 02:56:42 PM PDT 24 |
| Finished | May 26 03:00:32 PM PDT 24 |
| Peak memory | 263380 kb |
| Host | smart-0168857e-650d-47f2-ae98-a2985e586e18 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=38648481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.38648481 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/23.kmac_test_vectors_kmac.1766136895 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 251678697 ps |
| CPU time | 4.12 seconds |
| Started | May 26 02:56:41 PM PDT 24 |
| Finished | May 26 02:56:46 PM PDT 24 |
| Peak memory | 215520 kb |
| Host | smart-070ad55c-84f9-48f4-add3-4001642bd436 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766136895 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.kmac_test_vectors_kmac.1766136895 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1651112143 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 171354173 ps |
| CPU time | 4.65 seconds |
| Started | May 26 02:56:43 PM PDT 24 |
| Finished | May 26 02:56:49 PM PDT 24 |
| Peak memory | 215508 kb |
| Host | smart-2b49ad89-b112-4d55-8a17-26883aca6ae4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651112143 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1651112143 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/23.kmac_test_vectors_sha3_224.2084771855 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 97469793968 ps |
| CPU time | 1843.68 seconds |
| Started | May 26 02:56:41 PM PDT 24 |
| Finished | May 26 03:27:26 PM PDT 24 |
| Peak memory | 374684 kb |
| Host | smart-aea60705-8aee-499f-bbbc-927955fc1357 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2084771855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.2084771855 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/23.kmac_test_vectors_sha3_256.318131671 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 94443316390 ps |
| CPU time | 1982.51 seconds |
| Started | May 26 02:56:44 PM PDT 24 |
| Finished | May 26 03:29:47 PM PDT 24 |
| Peak memory | 378088 kb |
| Host | smart-2415dfb1-a3af-4ee3-9974-72c14bc8b84e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=318131671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.318131671 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/23.kmac_test_vectors_sha3_384.1582478250 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 28129086035 ps |
| CPU time | 1291.24 seconds |
| Started | May 26 02:56:43 PM PDT 24 |
| Finished | May 26 03:18:15 PM PDT 24 |
| Peak memory | 332240 kb |
| Host | smart-e95d90db-819b-414a-b1d1-6d4bbd651342 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1582478250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.1582478250 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/23.kmac_test_vectors_sha3_512.2445197578 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 39403076950 ps |
| CPU time | 837.38 seconds |
| Started | May 26 02:56:43 PM PDT 24 |
| Finished | May 26 03:10:41 PM PDT 24 |
| Peak memory | 301908 kb |
| Host | smart-b6fe298e-19b5-489e-87a2-0814ae5dcaf3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2445197578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2445197578 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/23.kmac_test_vectors_shake_128.3250083816 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3446958845115 ps |
| CPU time | 5631.19 seconds |
| Started | May 26 02:56:42 PM PDT 24 |
| Finished | May 26 04:30:35 PM PDT 24 |
| Peak memory | 651024 kb |
| Host | smart-31879696-77e1-4c2e-921b-83282a358a6a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3250083816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3250083816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/23.kmac_test_vectors_shake_256.4016425979 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 87015244355 ps |
| CPU time | 3433.37 seconds |
| Started | May 26 02:56:42 PM PDT 24 |
| Finished | May 26 03:53:57 PM PDT 24 |
| Peak memory | 565432 kb |
| Host | smart-9307df51-638f-43ee-b23d-e6e0b210f720 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4016425979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.4016425979 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/23.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/24.kmac_alert_test.1146189942 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 16786563 ps |
| CPU time | 0.82 seconds |
| Started | May 26 02:56:50 PM PDT 24 |
| Finished | May 26 02:56:52 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-a3619df1-ae6a-4284-8c8f-6f335e42fc40 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146189942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.1146189942 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/24.kmac_burst_write.885376566 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5225072843 ps |
| CPU time | 182.76 seconds |
| Started | May 26 02:56:49 PM PDT 24 |
| Finished | May 26 02:59:53 PM PDT 24 |
| Peak memory | 225184 kb |
| Host | smart-4910542b-a501-4782-b8e6-95dba2d175cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885376566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.885376566 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/24.kmac_entropy_refresh.4171372490 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 24976281407 ps |
| CPU time | 243.17 seconds |
| Started | May 26 02:56:49 PM PDT 24 |
| Finished | May 26 03:00:53 PM PDT 24 |
| Peak memory | 238992 kb |
| Host | smart-ba620d3b-3b71-4fd1-b60d-e92928688231 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171372490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.4171372490 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/24.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/24.kmac_error.233001953 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 5217975829 ps |
| CPU time | 93.82 seconds |
| Started | May 26 02:56:57 PM PDT 24 |
| Finished | May 26 02:58:31 PM PDT 24 |
| Peak memory | 240136 kb |
| Host | smart-22f48f52-71bd-48d1-8b2d-0a1c7dceb501 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233001953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.233001953 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_error/latest |
| Test location | /workspace/coverage/default/24.kmac_key_error.4011984228 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 506341231 ps |
| CPU time | 3.2 seconds |
| Started | May 26 02:56:56 PM PDT 24 |
| Finished | May 26 02:57:01 PM PDT 24 |
| Peak memory | 207108 kb |
| Host | smart-4eee0657-e178-4802-b385-3e294baafb34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011984228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.4011984228 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_key_error/latest |
| Test location | /workspace/coverage/default/24.kmac_lc_escalation.1059745381 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 77154526 ps |
| CPU time | 1.41 seconds |
| Started | May 26 02:56:56 PM PDT 24 |
| Finished | May 26 02:56:59 PM PDT 24 |
| Peak memory | 215352 kb |
| Host | smart-612dc94c-2360-47a2-aa6c-f0559e970555 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059745381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1059745381 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/24.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/24.kmac_long_msg_and_output.1571526852 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 337931655145 ps |
| CPU time | 1838.42 seconds |
| Started | May 26 02:56:48 PM PDT 24 |
| Finished | May 26 03:27:27 PM PDT 24 |
| Peak memory | 391392 kb |
| Host | smart-f7636377-d52e-4e17-a9af-c2f98aa2cda2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571526852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a nd_output.1571526852 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/24.kmac_sideload.1759739752 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 986993603 ps |
| CPU time | 79.29 seconds |
| Started | May 26 02:56:49 PM PDT 24 |
| Finished | May 26 02:58:09 PM PDT 24 |
| Peak memory | 234412 kb |
| Host | smart-7ed0ab9a-1cc5-476b-b7c5-253b5096af93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759739752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1759739752 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_sideload/latest |
| Test location | /workspace/coverage/default/24.kmac_smoke.3326226467 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 157543817 ps |
| CPU time | 8.34 seconds |
| Started | May 26 02:56:51 PM PDT 24 |
| Finished | May 26 02:57:00 PM PDT 24 |
| Peak memory | 218408 kb |
| Host | smart-2f2d4aa3-5a88-4940-a966-713c3c2f55ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326226467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3326226467 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_smoke/latest |
| Test location | /workspace/coverage/default/24.kmac_stress_all.1202489593 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 37230600265 ps |
| CPU time | 751.61 seconds |
| Started | May 26 02:56:50 PM PDT 24 |
| Finished | May 26 03:09:23 PM PDT 24 |
| Peak memory | 330852 kb |
| Host | smart-122a8afe-96d1-402e-a301-8bc944a0e2f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1202489593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1202489593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/24.kmac_test_vectors_kmac.3090601042 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 69391209 ps |
| CPU time | 3.9 seconds |
| Started | May 26 02:56:51 PM PDT 24 |
| Finished | May 26 02:56:55 PM PDT 24 |
| Peak memory | 215644 kb |
| Host | smart-1e05b31c-a43f-4147-bc1f-936498f403c4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090601042 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.kmac_test_vectors_kmac.3090601042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.2052314262 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 237439004 ps |
| CPU time | 3.99 seconds |
| Started | May 26 02:56:52 PM PDT 24 |
| Finished | May 26 02:56:56 PM PDT 24 |
| Peak memory | 215596 kb |
| Host | smart-7c8bbed1-58bd-4d3a-949d-50446296d418 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052314262 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.2052314262 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/24.kmac_test_vectors_sha3_224.1047425764 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 132320571654 ps |
| CPU time | 2085.21 seconds |
| Started | May 26 02:56:48 PM PDT 24 |
| Finished | May 26 03:31:35 PM PDT 24 |
| Peak memory | 399380 kb |
| Host | smart-5263ae27-0931-47fc-8cb5-09e0e871b8ad |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1047425764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.1047425764 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/24.kmac_test_vectors_sha3_256.3239013284 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 18288316287 ps |
| CPU time | 1434.34 seconds |
| Started | May 26 02:56:48 PM PDT 24 |
| Finished | May 26 03:20:44 PM PDT 24 |
| Peak memory | 370112 kb |
| Host | smart-7c656e14-45f6-4a59-b3e8-38bc8f65708c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3239013284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.3239013284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/24.kmac_test_vectors_sha3_384.45336725 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 190501274760 ps |
| CPU time | 1297.82 seconds |
| Started | May 26 02:56:50 PM PDT 24 |
| Finished | May 26 03:18:28 PM PDT 24 |
| Peak memory | 328072 kb |
| Host | smart-f2925831-3e98-406b-af8a-2d9f2b10e4a7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=45336725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.45336725 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/24.kmac_test_vectors_sha3_512.3942185498 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 33173020208 ps |
| CPU time | 868.74 seconds |
| Started | May 26 02:56:49 PM PDT 24 |
| Finished | May 26 03:11:19 PM PDT 24 |
| Peak memory | 293608 kb |
| Host | smart-3dc33e6c-35ae-4a62-9ec4-3d29dcced819 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3942185498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3942185498 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/24.kmac_test_vectors_shake_128.331972435 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 52093912649 ps |
| CPU time | 4108.86 seconds |
| Started | May 26 02:56:57 PM PDT 24 |
| Finished | May 26 04:05:27 PM PDT 24 |
| Peak memory | 643780 kb |
| Host | smart-349b09cd-2586-45c5-ade6-a506052dfbfa |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=331972435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.331972435 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/24.kmac_test_vectors_shake_256.3441894423 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 606503419648 ps |
| CPU time | 4185.05 seconds |
| Started | May 26 02:56:49 PM PDT 24 |
| Finished | May 26 04:06:35 PM PDT 24 |
| Peak memory | 562100 kb |
| Host | smart-904b9081-a883-488d-857f-eef575f9e6d1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3441894423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.3441894423 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/24.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/25.kmac_alert_test.216207058 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 222761049 ps |
| CPU time | 0.85 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 02:57:07 PM PDT 24 |
| Peak memory | 205036 kb |
| Host | smart-8179f930-a03a-4eae-bfc7-0a9108f1549c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216207058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.216207058 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/25.kmac_app.2763905389 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 16686176247 ps |
| CPU time | 206.48 seconds |
| Started | May 26 02:56:55 PM PDT 24 |
| Finished | May 26 03:00:23 PM PDT 24 |
| Peak memory | 240152 kb |
| Host | smart-b537a28a-57bb-4c36-a12b-017dc5dd1e96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763905389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2763905389 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_app/latest |
| Test location | /workspace/coverage/default/25.kmac_burst_write.3983046360 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 25896437922 ps |
| CPU time | 532.56 seconds |
| Started | May 26 02:56:48 PM PDT 24 |
| Finished | May 26 03:05:41 PM PDT 24 |
| Peak memory | 230844 kb |
| Host | smart-8684c6ac-80e7-4ab0-a429-2c3b92b212a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3983046360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.3983046360 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/25.kmac_entropy_refresh.1342986953 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 10088092456 ps |
| CPU time | 104.34 seconds |
| Started | May 26 02:56:55 PM PDT 24 |
| Finished | May 26 02:58:40 PM PDT 24 |
| Peak memory | 231956 kb |
| Host | smart-6df2870d-4abf-4d5b-a137-5a79054dc652 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342986953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1342986953 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/25.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/25.kmac_key_error.2949944529 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 797604096 ps |
| CPU time | 4.16 seconds |
| Started | May 26 02:56:55 PM PDT 24 |
| Finished | May 26 02:57:00 PM PDT 24 |
| Peak memory | 207112 kb |
| Host | smart-b1abf649-309d-48e1-a88f-0904187000dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949944529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2949944529 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_key_error/latest |
| Test location | /workspace/coverage/default/25.kmac_lc_escalation.623736663 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5402947591 ps |
| CPU time | 13.22 seconds |
| Started | May 26 02:56:57 PM PDT 24 |
| Finished | May 26 02:57:11 PM PDT 24 |
| Peak memory | 226032 kb |
| Host | smart-a68eaa1f-c0e9-4871-95b7-cf314fde3dea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623736663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.623736663 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/25.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/25.kmac_long_msg_and_output.540641485 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 67940701425 ps |
| CPU time | 1391.38 seconds |
| Started | May 26 02:56:56 PM PDT 24 |
| Finished | May 26 03:20:09 PM PDT 24 |
| Peak memory | 377136 kb |
| Host | smart-efc73919-2121-44d4-bb59-e161eb487a64 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540641485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an d_output.540641485 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/25.kmac_sideload.4128241156 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 68257504236 ps |
| CPU time | 325.78 seconds |
| Started | May 26 02:56:51 PM PDT 24 |
| Finished | May 26 03:02:18 PM PDT 24 |
| Peak memory | 243872 kb |
| Host | smart-120d0d4b-9ebf-4872-b270-8db31a8dbc88 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128241156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.4128241156 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_sideload/latest |
| Test location | /workspace/coverage/default/25.kmac_smoke.2579964954 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 692899740 ps |
| CPU time | 17.45 seconds |
| Started | May 26 02:56:57 PM PDT 24 |
| Finished | May 26 02:57:15 PM PDT 24 |
| Peak memory | 216692 kb |
| Host | smart-7019dcfe-8c91-49a7-9a21-ef0c30a40630 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579964954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.2579964954 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_smoke/latest |
| Test location | /workspace/coverage/default/25.kmac_stress_all.2375471793 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 58647779167 ps |
| CPU time | 936.93 seconds |
| Started | May 26 02:56:55 PM PDT 24 |
| Finished | May 26 03:12:33 PM PDT 24 |
| Peak memory | 368044 kb |
| Host | smart-f7cff56c-2184-498a-a49f-4e849ff745ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2375471793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2375471793 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/25.kmac_stress_all_with_rand_reset.3226425779 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 16789444008 ps |
| CPU time | 301.63 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 03:02:07 PM PDT 24 |
| Peak memory | 241496 kb |
| Host | smart-40ba3097-9a8c-4a2a-b2a6-4ee814437318 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3226425779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.3226425779 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.kmac_test_vectors_kmac.3599388248 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 71379465 ps |
| CPU time | 3.93 seconds |
| Started | May 26 02:56:57 PM PDT 24 |
| Finished | May 26 02:57:02 PM PDT 24 |
| Peak memory | 215488 kb |
| Host | smart-265cca33-bfa9-469f-8a8f-445386f31910 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599388248 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.kmac_test_vectors_kmac.3599388248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.4072500850 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 720293966 ps |
| CPU time | 4.53 seconds |
| Started | May 26 02:56:55 PM PDT 24 |
| Finished | May 26 02:57:01 PM PDT 24 |
| Peak memory | 215540 kb |
| Host | smart-66641c34-81ec-4a9e-9afd-6639b0123d7e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072500850 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_kmac_xof.4072500850 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/25.kmac_test_vectors_sha3_224.460730972 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 135868288931 ps |
| CPU time | 1935.57 seconds |
| Started | May 26 02:56:55 PM PDT 24 |
| Finished | May 26 03:29:11 PM PDT 24 |
| Peak memory | 393968 kb |
| Host | smart-ecc3978d-e3b1-4522-83bb-fd8991b2adae |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=460730972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.460730972 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/25.kmac_test_vectors_sha3_256.4190719816 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 73890143616 ps |
| CPU time | 1430.79 seconds |
| Started | May 26 02:56:56 PM PDT 24 |
| Finished | May 26 03:20:48 PM PDT 24 |
| Peak memory | 374336 kb |
| Host | smart-2888ac0a-8cfe-4df2-99c9-189a79c3e6c9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4190719816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.4190719816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/25.kmac_test_vectors_sha3_384.3916212862 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 278886303537 ps |
| CPU time | 1476.34 seconds |
| Started | May 26 02:56:55 PM PDT 24 |
| Finished | May 26 03:21:33 PM PDT 24 |
| Peak memory | 331984 kb |
| Host | smart-98f2498d-4f27-48e3-a65e-4936d267a569 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3916212862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3916212862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/25.kmac_test_vectors_sha3_512.2083499095 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 19995557385 ps |
| CPU time | 837.73 seconds |
| Started | May 26 02:56:56 PM PDT 24 |
| Finished | May 26 03:10:55 PM PDT 24 |
| Peak memory | 296760 kb |
| Host | smart-e329569b-d87d-4825-8ec3-aa1b797efde9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2083499095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.2083499095 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/25.kmac_test_vectors_shake_128.2221163128 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 51617171577 ps |
| CPU time | 4291.01 seconds |
| Started | May 26 02:56:57 PM PDT 24 |
| Finished | May 26 04:08:30 PM PDT 24 |
| Peak memory | 643892 kb |
| Host | smart-85b142b3-1b8c-486c-acf9-328915377fa6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2221163128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2221163128 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/25.kmac_test_vectors_shake_256.745416108 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 45638296574 ps |
| CPU time | 3352.21 seconds |
| Started | May 26 02:56:55 PM PDT 24 |
| Finished | May 26 03:52:49 PM PDT 24 |
| Peak memory | 571376 kb |
| Host | smart-929de525-824a-474a-b782-b33983e15182 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=745416108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.745416108 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/25.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/26.kmac_alert_test.1694961339 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 19113412 ps |
| CPU time | 0.85 seconds |
| Started | May 26 02:57:13 PM PDT 24 |
| Finished | May 26 02:57:15 PM PDT 24 |
| Peak memory | 205032 kb |
| Host | smart-2b7beef1-1ba6-4974-a81a-ec036c939852 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694961339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1694961339 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/26.kmac_burst_write.3271875506 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 8476654947 ps |
| CPU time | 291.66 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 03:01:57 PM PDT 24 |
| Peak memory | 227036 kb |
| Host | smart-50aeeaad-52d8-45c9-95a0-2fe4ce68f6be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271875506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3271875506 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/26.kmac_entropy_refresh.1292041901 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 5614283145 ps |
| CPU time | 87.96 seconds |
| Started | May 26 02:57:03 PM PDT 24 |
| Finished | May 26 02:58:32 PM PDT 24 |
| Peak memory | 229820 kb |
| Host | smart-3252461e-d990-4eaf-9e15-e8b6df3dd3ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292041901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1292041901 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/26.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/26.kmac_error.3192574873 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7512793185 ps |
| CPU time | 148.94 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 02:59:34 PM PDT 24 |
| Peak memory | 248396 kb |
| Host | smart-eecb5fb6-832a-4abe-94ce-b526cec4ac5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192574873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3192574873 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_error/latest |
| Test location | /workspace/coverage/default/26.kmac_key_error.1432785831 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 5995032868 ps |
| CPU time | 7.3 seconds |
| Started | May 26 02:57:10 PM PDT 24 |
| Finished | May 26 02:57:19 PM PDT 24 |
| Peak memory | 215332 kb |
| Host | smart-cdfa8045-ebbe-4aee-a34f-d9584fb48d83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432785831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1432785831 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_key_error/latest |
| Test location | /workspace/coverage/default/26.kmac_lc_escalation.3982518957 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 37072089 ps |
| CPU time | 1.26 seconds |
| Started | May 26 02:57:11 PM PDT 24 |
| Finished | May 26 02:57:14 PM PDT 24 |
| Peak memory | 218976 kb |
| Host | smart-40cabe53-1f33-461e-817a-58b86ba4a15f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982518957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3982518957 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/26.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/26.kmac_long_msg_and_output.3754329912 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 33121046597 ps |
| CPU time | 744.4 seconds |
| Started | May 26 02:57:03 PM PDT 24 |
| Finished | May 26 03:09:29 PM PDT 24 |
| Peak memory | 293604 kb |
| Host | smart-d4787b0f-f667-4e0a-be67-f004c1471a56 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754329912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a nd_output.3754329912 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/26.kmac_sideload.763277563 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 4652214169 ps |
| CPU time | 48.79 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 02:57:54 PM PDT 24 |
| Peak memory | 220408 kb |
| Host | smart-a661757a-b1f4-4ed4-99bd-fddac044a1c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763277563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.763277563 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_sideload/latest |
| Test location | /workspace/coverage/default/26.kmac_smoke.1283822510 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 1111655304 ps |
| CPU time | 24.51 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 02:57:30 PM PDT 24 |
| Peak memory | 216804 kb |
| Host | smart-777d5b73-7ed6-41dc-94d7-1ff7d03ec6e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283822510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1283822510 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_smoke/latest |
| Test location | /workspace/coverage/default/26.kmac_stress_all.1915047837 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 208495576353 ps |
| CPU time | 2177.83 seconds |
| Started | May 26 02:57:12 PM PDT 24 |
| Finished | May 26 03:33:31 PM PDT 24 |
| Peak memory | 452004 kb |
| Host | smart-6ad3c222-10b9-40ef-89c4-e00c02097587 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1915047837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.1915047837 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/26.kmac_test_vectors_kmac.1685871365 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 311536890 ps |
| CPU time | 3.92 seconds |
| Started | May 26 02:57:05 PM PDT 24 |
| Finished | May 26 02:57:10 PM PDT 24 |
| Peak memory | 215636 kb |
| Host | smart-583138a6-f73f-4d44-a422-f0cd0d30fdb7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685871365 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.1685871365 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1155911298 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 350242064 ps |
| CPU time | 4.77 seconds |
| Started | May 26 02:57:08 PM PDT 24 |
| Finished | May 26 02:57:14 PM PDT 24 |
| Peak memory | 215528 kb |
| Host | smart-473a3384-5f10-49c1-a27c-852ef7d37f9c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155911298 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1155911298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/26.kmac_test_vectors_sha3_224.1149628351 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 19778114055 ps |
| CPU time | 1563.39 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 03:23:09 PM PDT 24 |
| Peak memory | 398872 kb |
| Host | smart-f35ce4b4-2bc7-444d-a38f-472f2753becd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1149628351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.1149628351 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/26.kmac_test_vectors_sha3_256.3189023206 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 387237080673 ps |
| CPU time | 2039.34 seconds |
| Started | May 26 02:57:05 PM PDT 24 |
| Finished | May 26 03:31:06 PM PDT 24 |
| Peak memory | 378032 kb |
| Host | smart-da763d84-e131-48e7-8770-9a3244b61fb8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3189023206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.3189023206 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/26.kmac_test_vectors_sha3_384.3807632381 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 144229428073 ps |
| CPU time | 1364.44 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 03:19:50 PM PDT 24 |
| Peak memory | 331324 kb |
| Host | smart-349a69b3-7bfb-420a-846a-ac518a05163e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3807632381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3807632381 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3787461065 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 67808427715 ps |
| CPU time | 926.49 seconds |
| Started | May 26 02:57:03 PM PDT 24 |
| Finished | May 26 03:12:31 PM PDT 24 |
| Peak memory | 294120 kb |
| Host | smart-d32e8482-2666-48c8-b27a-f866a7cd4ccd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3787461065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3787461065 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/26.kmac_test_vectors_shake_256.2908379003 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 44866590313 ps |
| CPU time | 3521.15 seconds |
| Started | May 26 02:57:04 PM PDT 24 |
| Finished | May 26 03:55:47 PM PDT 24 |
| Peak memory | 556940 kb |
| Host | smart-d9c1ed9b-62e0-46fe-9bf9-938d1e04f1c3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2908379003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.2908379003 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/26.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/27.kmac_alert_test.564824251 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 22817809 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:57:18 PM PDT 24 |
| Finished | May 26 02:57:19 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-60583ac3-5fa7-4259-b596-a35202129762 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564824251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.564824251 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/27.kmac_app.192088858 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 7725471417 ps |
| CPU time | 240.65 seconds |
| Started | May 26 02:57:11 PM PDT 24 |
| Finished | May 26 03:01:13 PM PDT 24 |
| Peak memory | 241552 kb |
| Host | smart-8ca386e8-b0cc-490a-aa8f-b85f5c1342ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192088858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.192088858 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_app/latest |
| Test location | /workspace/coverage/default/27.kmac_burst_write.3066814698 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 326541296 ps |
| CPU time | 9.62 seconds |
| Started | May 26 02:57:10 PM PDT 24 |
| Finished | May 26 02:57:20 PM PDT 24 |
| Peak memory | 217972 kb |
| Host | smart-1013a801-50e3-48f4-9c3c-ab231e22fe7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066814698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3066814698 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/27.kmac_entropy_refresh.3350826535 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 81859479632 ps |
| CPU time | 277.24 seconds |
| Started | May 26 02:57:13 PM PDT 24 |
| Finished | May 26 03:01:51 PM PDT 24 |
| Peak memory | 242456 kb |
| Host | smart-baa9ff1e-1dd0-4729-9343-f40e9870022c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350826535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3350826535 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/27.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/27.kmac_error.168630883 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 8936840085 ps |
| CPU time | 231.94 seconds |
| Started | May 26 02:57:10 PM PDT 24 |
| Finished | May 26 03:01:04 PM PDT 24 |
| Peak memory | 249420 kb |
| Host | smart-ed547b4b-ec57-4109-a381-d298b52bea67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168630883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.168630883 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_error/latest |
| Test location | /workspace/coverage/default/27.kmac_key_error.1366151521 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 613973176 ps |
| CPU time | 2.18 seconds |
| Started | May 26 02:57:19 PM PDT 24 |
| Finished | May 26 02:57:21 PM PDT 24 |
| Peak memory | 215340 kb |
| Host | smart-e0a5f076-3355-4424-ae6e-1c9f0be907d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366151521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1366151521 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_key_error/latest |
| Test location | /workspace/coverage/default/27.kmac_lc_escalation.2916034187 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 62602302 ps |
| CPU time | 1.13 seconds |
| Started | May 26 02:57:22 PM PDT 24 |
| Finished | May 26 02:57:24 PM PDT 24 |
| Peak memory | 215352 kb |
| Host | smart-b404e9dd-8369-40c9-be17-f1db45332a74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916034187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2916034187 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/27.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/27.kmac_long_msg_and_output.561665686 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 142260168330 ps |
| CPU time | 2095.89 seconds |
| Started | May 26 02:57:12 PM PDT 24 |
| Finished | May 26 03:32:09 PM PDT 24 |
| Peak memory | 421076 kb |
| Host | smart-98fc3193-e5e6-45b5-8004-2e6661619ab9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561665686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an d_output.561665686 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/27.kmac_smoke.1628564060 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 881594672 ps |
| CPU time | 23.76 seconds |
| Started | May 26 02:57:10 PM PDT 24 |
| Finished | May 26 02:57:35 PM PDT 24 |
| Peak memory | 219160 kb |
| Host | smart-5a684405-f724-4383-8e48-3f5230978740 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628564060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1628564060 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_smoke/latest |
| Test location | /workspace/coverage/default/27.kmac_stress_all.1864929253 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 52999115971 ps |
| CPU time | 780.51 seconds |
| Started | May 26 02:57:17 PM PDT 24 |
| Finished | May 26 03:10:19 PM PDT 24 |
| Peak memory | 322456 kb |
| Host | smart-dbad5436-b82c-4206-a162-2eb1a7901533 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1864929253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1864929253 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/27.kmac_test_vectors_kmac.1789353245 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 87843435 ps |
| CPU time | 4.05 seconds |
| Started | May 26 02:57:13 PM PDT 24 |
| Finished | May 26 02:57:18 PM PDT 24 |
| Peak memory | 215568 kb |
| Host | smart-1dd6989e-64a4-499b-8560-ddf9b75a21b7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789353245 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.kmac_test_vectors_kmac.1789353245 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.4227413052 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 73447713 ps |
| CPU time | 3.91 seconds |
| Started | May 26 02:57:12 PM PDT 24 |
| Finished | May 26 02:57:17 PM PDT 24 |
| Peak memory | 215472 kb |
| Host | smart-a661541a-3296-4519-95fe-f6824cd337bf |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227413052 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.4227413052 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/27.kmac_test_vectors_sha3_224.2536361340 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 297190599050 ps |
| CPU time | 1840.19 seconds |
| Started | May 26 02:57:13 PM PDT 24 |
| Finished | May 26 03:27:55 PM PDT 24 |
| Peak memory | 394260 kb |
| Host | smart-974fe72f-5503-4138-9419-fa1a78702bf0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2536361340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.2536361340 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/27.kmac_test_vectors_sha3_256.475992463 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 247338984455 ps |
| CPU time | 1668.36 seconds |
| Started | May 26 02:57:11 PM PDT 24 |
| Finished | May 26 03:25:01 PM PDT 24 |
| Peak memory | 378152 kb |
| Host | smart-923144ac-5f28-476d-b208-e4086d4b59e0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=475992463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.475992463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/27.kmac_test_vectors_sha3_384.2218409031 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 85897583945 ps |
| CPU time | 1192.54 seconds |
| Started | May 26 02:57:12 PM PDT 24 |
| Finished | May 26 03:17:06 PM PDT 24 |
| Peak memory | 337032 kb |
| Host | smart-eccd15ee-85a5-4cdf-9fbd-6fb1164010e9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2218409031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.2218409031 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/27.kmac_test_vectors_sha3_512.2913424260 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 156667735556 ps |
| CPU time | 816.7 seconds |
| Started | May 26 02:57:11 PM PDT 24 |
| Finished | May 26 03:10:49 PM PDT 24 |
| Peak memory | 292552 kb |
| Host | smart-cb44009e-b6db-457c-857d-beda1af247b6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2913424260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.2913424260 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/27.kmac_test_vectors_shake_128.36120151 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1067953903936 ps |
| CPU time | 5830.2 seconds |
| Started | May 26 02:57:13 PM PDT 24 |
| Finished | May 26 04:34:24 PM PDT 24 |
| Peak memory | 648684 kb |
| Host | smart-48c173f9-b5c9-4b8c-b0ed-cb72b8cbf208 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=36120151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.36120151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/27.kmac_test_vectors_shake_256.1227869130 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 189406661303 ps |
| CPU time | 4094.98 seconds |
| Started | May 26 02:57:12 PM PDT 24 |
| Finished | May 26 04:05:28 PM PDT 24 |
| Peak memory | 566520 kb |
| Host | smart-ef68a0f3-2f7b-4217-94a9-06d564131623 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1227869130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1227869130 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/27.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/28.kmac_alert_test.4139626164 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 13318618 ps |
| CPU time | 0.78 seconds |
| Started | May 26 02:57:31 PM PDT 24 |
| Finished | May 26 02:57:33 PM PDT 24 |
| Peak memory | 204872 kb |
| Host | smart-891973ac-6a18-4703-a71b-1de87ddc2517 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139626164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.4139626164 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/28.kmac_app.4068821729 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 8389165091 ps |
| CPU time | 76.55 seconds |
| Started | May 26 02:57:25 PM PDT 24 |
| Finished | May 26 02:58:42 PM PDT 24 |
| Peak memory | 225664 kb |
| Host | smart-94feabac-d575-443f-b31f-695be16d880b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068821729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.4068821729 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_app/latest |
| Test location | /workspace/coverage/default/28.kmac_burst_write.2101355 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 615079216 ps |
| CPU time | 29.91 seconds |
| Started | May 26 02:57:18 PM PDT 24 |
| Finished | May 26 02:57:49 PM PDT 24 |
| Peak memory | 218976 kb |
| Host | smart-5100b464-0a7c-42d3-9960-edcfcf8a8b57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2101355 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/28.kmac_entropy_refresh.1940700330 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3601216807 ps |
| CPU time | 111.98 seconds |
| Started | May 26 02:57:29 PM PDT 24 |
| Finished | May 26 02:59:22 PM PDT 24 |
| Peak memory | 231964 kb |
| Host | smart-2bfb6cc1-da0c-41e3-b2b8-d83d9eeaf325 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940700330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1940700330 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/28.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/28.kmac_error.866389155 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 12913974100 ps |
| CPU time | 82.69 seconds |
| Started | May 26 02:57:27 PM PDT 24 |
| Finished | May 26 02:58:51 PM PDT 24 |
| Peak memory | 240124 kb |
| Host | smart-ab221121-7bbf-4060-a024-d824f06bc850 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866389155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.866389155 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_error/latest |
| Test location | /workspace/coverage/default/28.kmac_key_error.2554510797 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1260486020 ps |
| CPU time | 6.84 seconds |
| Started | May 26 02:57:29 PM PDT 24 |
| Finished | May 26 02:57:36 PM PDT 24 |
| Peak memory | 207108 kb |
| Host | smart-ae0e4e75-5708-49ab-9a61-8bee34f75b25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554510797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2554510797 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_key_error/latest |
| Test location | /workspace/coverage/default/28.kmac_lc_escalation.1700350852 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 47740291 ps |
| CPU time | 1.24 seconds |
| Started | May 26 02:57:26 PM PDT 24 |
| Finished | May 26 02:57:29 PM PDT 24 |
| Peak memory | 215352 kb |
| Host | smart-601d6388-b52c-4b3f-8cca-2759a6d23e59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700350852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1700350852 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/28.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/28.kmac_long_msg_and_output.2770761007 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 526051928591 ps |
| CPU time | 2985.12 seconds |
| Started | May 26 02:57:19 PM PDT 24 |
| Finished | May 26 03:47:05 PM PDT 24 |
| Peak memory | 470244 kb |
| Host | smart-730babb4-7018-44ab-8dcf-6be95524c608 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770761007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a nd_output.2770761007 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/28.kmac_sideload.1495383363 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 14152277767 ps |
| CPU time | 259.22 seconds |
| Started | May 26 02:57:22 PM PDT 24 |
| Finished | May 26 03:01:42 PM PDT 24 |
| Peak memory | 238020 kb |
| Host | smart-af86cf4b-3ff3-4580-89b2-3de6fb4315e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495383363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1495383363 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_sideload/latest |
| Test location | /workspace/coverage/default/28.kmac_smoke.3615024551 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1875554735 ps |
| CPU time | 41.78 seconds |
| Started | May 26 02:57:17 PM PDT 24 |
| Finished | May 26 02:57:59 PM PDT 24 |
| Peak memory | 217236 kb |
| Host | smart-c4054b92-de1d-41f7-ac93-ec428d834bb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615024551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.3615024551 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_smoke/latest |
| Test location | /workspace/coverage/default/28.kmac_stress_all.1788266768 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 4492938711 ps |
| CPU time | 231.36 seconds |
| Started | May 26 02:57:27 PM PDT 24 |
| Finished | May 26 03:01:19 PM PDT 24 |
| Peak memory | 272056 kb |
| Host | smart-924dfce2-9a40-4211-974e-b4aef3c6b259 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1788266768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1788266768 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/28.kmac_test_vectors_kmac.3991020696 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 168682036 ps |
| CPU time | 4.99 seconds |
| Started | May 26 02:57:26 PM PDT 24 |
| Finished | May 26 02:57:32 PM PDT 24 |
| Peak memory | 215480 kb |
| Host | smart-1108b49f-5749-42e1-8d10-60518856d219 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991020696 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.3991020696 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.2020139248 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 884694110 ps |
| CPU time | 4.66 seconds |
| Started | May 26 02:57:26 PM PDT 24 |
| Finished | May 26 02:57:31 PM PDT 24 |
| Peak memory | 215548 kb |
| Host | smart-55f810ae-f0ad-4fad-a961-90dfc749d46f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020139248 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac_xof.2020139248 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/28.kmac_test_vectors_sha3_224.2436908726 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 69354532985 ps |
| CPU time | 1832.78 seconds |
| Started | May 26 02:57:18 PM PDT 24 |
| Finished | May 26 03:27:52 PM PDT 24 |
| Peak memory | 401392 kb |
| Host | smart-6f1e8e14-68c6-4c3b-9aaa-cff0882dfa96 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2436908726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.2436908726 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/28.kmac_test_vectors_sha3_256.2026228051 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 95745678887 ps |
| CPU time | 1813.35 seconds |
| Started | May 26 02:57:25 PM PDT 24 |
| Finished | May 26 03:27:39 PM PDT 24 |
| Peak memory | 375600 kb |
| Host | smart-a90a9f2d-e41b-4954-a6b5-0f909e187fc0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2026228051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.2026228051 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/28.kmac_test_vectors_sha3_384.2033277519 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 28974460212 ps |
| CPU time | 1187.06 seconds |
| Started | May 26 02:57:25 PM PDT 24 |
| Finished | May 26 03:17:13 PM PDT 24 |
| Peak memory | 339664 kb |
| Host | smart-617edc59-f30a-40a2-b18c-b12c510d4fda |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2033277519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2033277519 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/28.kmac_test_vectors_sha3_512.3596108409 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 136567926184 ps |
| CPU time | 990.34 seconds |
| Started | May 26 02:57:26 PM PDT 24 |
| Finished | May 26 03:13:57 PM PDT 24 |
| Peak memory | 295460 kb |
| Host | smart-b991a18a-c5e4-4dfc-91fb-a3fb181898a7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3596108409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.3596108409 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/28.kmac_test_vectors_shake_128.444561949 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 203806932491 ps |
| CPU time | 4411.07 seconds |
| Started | May 26 02:57:27 PM PDT 24 |
| Finished | May 26 04:10:59 PM PDT 24 |
| Peak memory | 653256 kb |
| Host | smart-3fe1e05c-9f2e-4239-bcc4-0e144cfe5f32 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=444561949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.444561949 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/28.kmac_test_vectors_shake_256.2851230159 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 150399026411 ps |
| CPU time | 3946 seconds |
| Started | May 26 02:57:25 PM PDT 24 |
| Finished | May 26 04:03:12 PM PDT 24 |
| Peak memory | 554348 kb |
| Host | smart-0a49e53c-99df-45f2-a7d6-0a482dc45538 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2851230159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.2851230159 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/28.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/29.kmac_alert_test.2689215606 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 25055784 ps |
| CPU time | 0.81 seconds |
| Started | May 26 02:57:41 PM PDT 24 |
| Finished | May 26 02:57:44 PM PDT 24 |
| Peak memory | 204852 kb |
| Host | smart-4373417c-56be-45b9-bb1b-2b7f1a204e84 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689215606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2689215606 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/29.kmac_app.598859978 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 3656159580 ps |
| CPU time | 29.26 seconds |
| Started | May 26 02:57:34 PM PDT 24 |
| Finished | May 26 02:58:04 PM PDT 24 |
| Peak memory | 220164 kb |
| Host | smart-55bf4609-6def-456f-803b-6081fd190b50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598859978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.598859978 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_app/latest |
| Test location | /workspace/coverage/default/29.kmac_burst_write.1331514642 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 29086850979 ps |
| CPU time | 224.24 seconds |
| Started | May 26 02:57:40 PM PDT 24 |
| Finished | May 26 03:01:26 PM PDT 24 |
| Peak memory | 224488 kb |
| Host | smart-b9e586c7-2fd5-4086-9102-9fa58016e65d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1331514642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.1331514642 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/29.kmac_entropy_refresh.2620109075 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2460446128 ps |
| CPU time | 65.89 seconds |
| Started | May 26 02:57:41 PM PDT 24 |
| Finished | May 26 02:58:49 PM PDT 24 |
| Peak memory | 226080 kb |
| Host | smart-718f0732-9d18-4115-a03b-ccf445a60ab9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620109075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2620109075 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/29.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/29.kmac_error.3338897563 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 13676607155 ps |
| CPU time | 144.76 seconds |
| Started | May 26 02:57:33 PM PDT 24 |
| Finished | May 26 02:59:59 PM PDT 24 |
| Peak memory | 240200 kb |
| Host | smart-a8521ad7-09c5-4f87-874f-87f6a3ac3f07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338897563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3338897563 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_error/latest |
| Test location | /workspace/coverage/default/29.kmac_key_error.344982624 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 22678121645 ps |
| CPU time | 6.55 seconds |
| Started | May 26 02:57:40 PM PDT 24 |
| Finished | May 26 02:57:47 PM PDT 24 |
| Peak memory | 207160 kb |
| Host | smart-c1c27d5b-ad10-4123-b58c-6174f32047b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=344982624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.344982624 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_key_error/latest |
| Test location | /workspace/coverage/default/29.kmac_lc_escalation.3629122887 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 42033166 ps |
| CPU time | 1.11 seconds |
| Started | May 26 02:57:40 PM PDT 24 |
| Finished | May 26 02:57:42 PM PDT 24 |
| Peak memory | 215284 kb |
| Host | smart-5c1f638c-b089-4ec4-9431-c06267246a0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629122887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3629122887 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/29.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/29.kmac_long_msg_and_output.2658616329 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 77607361217 ps |
| CPU time | 1139.31 seconds |
| Started | May 26 02:57:40 PM PDT 24 |
| Finished | May 26 03:16:42 PM PDT 24 |
| Peak memory | 326592 kb |
| Host | smart-21fc2735-d114-4cb5-8b48-655577e4c831 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658616329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a nd_output.2658616329 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/29.kmac_sideload.13227681 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 8038547157 ps |
| CPU time | 195.61 seconds |
| Started | May 26 02:57:33 PM PDT 24 |
| Finished | May 26 03:00:49 PM PDT 24 |
| Peak memory | 235868 kb |
| Host | smart-65166025-6ad7-4e96-a0bc-817f03a7d8cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13227681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.13227681 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_sideload/latest |
| Test location | /workspace/coverage/default/29.kmac_smoke.3440751664 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 554954858 ps |
| CPU time | 15.86 seconds |
| Started | May 26 02:57:33 PM PDT 24 |
| Finished | May 26 02:57:49 PM PDT 24 |
| Peak memory | 221200 kb |
| Host | smart-3498e622-6033-46cb-93f3-a99276b76761 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440751664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3440751664 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_smoke/latest |
| Test location | /workspace/coverage/default/29.kmac_stress_all.3994029686 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 39919341263 ps |
| CPU time | 538.91 seconds |
| Started | May 26 02:57:41 PM PDT 24 |
| Finished | May 26 03:06:42 PM PDT 24 |
| Peak memory | 315480 kb |
| Host | smart-58a5d61e-06a0-4fb6-9cbd-881f5ec88287 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3994029686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3994029686 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/29.kmac_test_vectors_kmac.2273393832 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 908633625 ps |
| CPU time | 4.32 seconds |
| Started | May 26 02:57:33 PM PDT 24 |
| Finished | May 26 02:57:38 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-16fbc8ad-7ff3-4540-bc22-56539b9ad20e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273393832 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.kmac_test_vectors_kmac.2273393832 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.1262795212 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 268745543 ps |
| CPU time | 4.09 seconds |
| Started | May 26 02:57:34 PM PDT 24 |
| Finished | May 26 02:57:39 PM PDT 24 |
| Peak memory | 215464 kb |
| Host | smart-d5a19e7b-44df-4dda-a477-dc49957f4fe2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262795212 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.1262795212 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/29.kmac_test_vectors_sha3_224.349011968 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 131011305916 ps |
| CPU time | 1772.76 seconds |
| Started | May 26 02:57:41 PM PDT 24 |
| Finished | May 26 03:27:15 PM PDT 24 |
| Peak memory | 395880 kb |
| Host | smart-954b6df5-f326-410c-801b-3d0a9d76e97a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=349011968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.349011968 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/29.kmac_test_vectors_sha3_256.155744689 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 302298772325 ps |
| CPU time | 1532.39 seconds |
| Started | May 26 02:57:40 PM PDT 24 |
| Finished | May 26 03:23:13 PM PDT 24 |
| Peak memory | 389448 kb |
| Host | smart-ab894718-634a-4f1a-adcf-6d69ce523992 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=155744689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.155744689 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/29.kmac_test_vectors_sha3_384.1872906204 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 14321534445 ps |
| CPU time | 1119.61 seconds |
| Started | May 26 02:57:40 PM PDT 24 |
| Finished | May 26 03:16:21 PM PDT 24 |
| Peak memory | 337216 kb |
| Host | smart-753733e8-cfa5-49b7-8c71-5588b3d9e009 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1872906204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.1872906204 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/29.kmac_test_vectors_sha3_512.3426913879 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 140300470864 ps |
| CPU time | 864.66 seconds |
| Started | May 26 02:57:41 PM PDT 24 |
| Finished | May 26 03:12:08 PM PDT 24 |
| Peak memory | 292792 kb |
| Host | smart-8e1fff57-7738-46cc-9e72-5bde1f0988ba |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3426913879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.3426913879 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/29.kmac_test_vectors_shake_128.2014139855 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1026775582269 ps |
| CPU time | 5462.69 seconds |
| Started | May 26 02:57:34 PM PDT 24 |
| Finished | May 26 04:28:38 PM PDT 24 |
| Peak memory | 650440 kb |
| Host | smart-c83048d4-3bd5-4f32-bc08-ed6055440a4e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2014139855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2014139855 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/29.kmac_test_vectors_shake_256.101605383 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 159827958352 ps |
| CPU time | 3671.7 seconds |
| Started | May 26 02:57:34 PM PDT 24 |
| Finished | May 26 03:58:47 PM PDT 24 |
| Peak memory | 559756 kb |
| Host | smart-a60c2108-983f-4d25-8662-cae5500b2bd7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=101605383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.101605383 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/29.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/3.kmac_alert_test.3137927972 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 32031445 ps |
| CPU time | 0.84 seconds |
| Started | May 26 02:55:07 PM PDT 24 |
| Finished | May 26 02:55:10 PM PDT 24 |
| Peak memory | 204864 kb |
| Host | smart-b71b9c30-246e-49da-8e89-b3ee2b7c6f29 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137927972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3137927972 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/3.kmac_app.1283748804 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5810374395 ps |
| CPU time | 201.67 seconds |
| Started | May 26 02:55:04 PM PDT 24 |
| Finished | May 26 02:58:28 PM PDT 24 |
| Peak memory | 241560 kb |
| Host | smart-daf6dbfb-d5c4-4850-8a19-bf47e6463702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283748804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.1283748804 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_app/latest |
| Test location | /workspace/coverage/default/3.kmac_app_with_partial_data.2136549315 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 7271041707 ps |
| CPU time | 52.59 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 02:56:00 PM PDT 24 |
| Peak memory | 223124 kb |
| Host | smart-8dd345b8-f707-49ce-9b57-ab8bf2edbe48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136549315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2136549315 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/3.kmac_burst_write.3920814531 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 19719996688 ps |
| CPU time | 615.04 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 03:05:18 PM PDT 24 |
| Peak memory | 231296 kb |
| Host | smart-8a273b21-9e75-4d36-bd72-adb2997fe395 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920814531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3920814531 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/3.kmac_edn_timeout_error.1314453098 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1503534897 ps |
| CPU time | 11.4 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:55:30 PM PDT 24 |
| Peak memory | 223396 kb |
| Host | smart-7107428f-5cd0-4ffb-8187-e067d3ebbef8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1314453098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1314453098 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/3.kmac_entropy_mode_error.932391982 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1382934886 ps |
| CPU time | 24.24 seconds |
| Started | May 26 02:55:03 PM PDT 24 |
| Finished | May 26 02:55:30 PM PDT 24 |
| Peak memory | 219820 kb |
| Host | smart-ef303585-da69-4eaa-a81d-c5484680e515 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=932391982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.932391982 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/3.kmac_entropy_refresh.4293427345 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 11490569026 ps |
| CPU time | 120.83 seconds |
| Started | May 26 02:55:09 PM PDT 24 |
| Finished | May 26 02:57:12 PM PDT 24 |
| Peak memory | 231768 kb |
| Host | smart-53233352-92e9-4133-9295-140b7bbc8b5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293427345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.4293427345 +enable_masking=0 +s w_key_masked=0 |
| Directory | /workspace/3.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/3.kmac_error.592583212 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 8252482100 ps |
| CPU time | 164.32 seconds |
| Started | May 26 02:55:07 PM PDT 24 |
| Finished | May 26 02:57:54 PM PDT 24 |
| Peak memory | 248476 kb |
| Host | smart-53c73101-9e3c-4f5e-8f53-7bad9304aadf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592583212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.592583212 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_error/latest |
| Test location | /workspace/coverage/default/3.kmac_key_error.3311366149 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 543828992 ps |
| CPU time | 2.05 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 02:55:10 PM PDT 24 |
| Peak memory | 215192 kb |
| Host | smart-ed4d3bbd-9759-450b-8fcf-a00c12a52514 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311366149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3311366149 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_key_error/latest |
| Test location | /workspace/coverage/default/3.kmac_long_msg_and_output.1780980298 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 469625514233 ps |
| CPU time | 856.09 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 03:09:19 PM PDT 24 |
| Peak memory | 281616 kb |
| Host | smart-cdb8145f-9e15-4d60-9343-54593b540abf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780980298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an d_output.1780980298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/3.kmac_mubi.2401923925 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 122731045436 ps |
| CPU time | 226.61 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 02:58:51 PM PDT 24 |
| Peak memory | 241584 kb |
| Host | smart-35884112-4a9f-47ca-a085-83f18c17c74f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401923925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.2401923925 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_mubi/latest |
| Test location | /workspace/coverage/default/3.kmac_sec_cm.238283550 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 15290817957 ps |
| CPU time | 60.87 seconds |
| Started | May 26 02:55:01 PM PDT 24 |
| Finished | May 26 02:56:05 PM PDT 24 |
| Peak memory | 253248 kb |
| Host | smart-2586e4e9-a9e1-41b1-9ac3-88726c0ccd2f |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238283550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.238283550 +enable_masking =0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_sec_cm/latest |
| Test location | /workspace/coverage/default/3.kmac_sideload.3491312442 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1753180058 ps |
| CPU time | 68.08 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:56:26 PM PDT 24 |
| Peak memory | 224780 kb |
| Host | smart-5639d4fb-b8b3-4226-af35-6302902ad7c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491312442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3491312442 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_sideload/latest |
| Test location | /workspace/coverage/default/3.kmac_smoke.4275625518 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 465484149 ps |
| CPU time | 24.42 seconds |
| Started | May 26 02:55:02 PM PDT 24 |
| Finished | May 26 02:55:29 PM PDT 24 |
| Peak memory | 218108 kb |
| Host | smart-35530fea-5868-4ab7-91e7-a66a5ab92c73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275625518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.4275625518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_smoke/latest |
| Test location | /workspace/coverage/default/3.kmac_stress_all.450171604 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 149320175837 ps |
| CPU time | 719.47 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 03:07:18 PM PDT 24 |
| Peak memory | 332116 kb |
| Host | smart-66f3e674-2733-4035-85fb-b83807763b92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=450171604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.450171604 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/3.kmac_test_vectors_kmac.2399785802 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 67711174 ps |
| CPU time | 3.83 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 02:55:06 PM PDT 24 |
| Peak memory | 215528 kb |
| Host | smart-93d8aa7e-7213-4c1c-8851-4d7e657b6c0a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399785802 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.kmac_test_vectors_kmac.2399785802 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.3604536501 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1057294637 ps |
| CPU time | 5.71 seconds |
| Started | May 26 02:55:04 PM PDT 24 |
| Finished | May 26 02:55:12 PM PDT 24 |
| Peak memory | 215540 kb |
| Host | smart-788b9b7f-4a96-4c3d-97f7-4e88863152e6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604536501 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3604536501 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/3.kmac_test_vectors_sha3_224.2704928349 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 197348492886 ps |
| CPU time | 1941.91 seconds |
| Started | May 26 02:54:58 PM PDT 24 |
| Finished | May 26 03:27:23 PM PDT 24 |
| Peak memory | 376072 kb |
| Host | smart-c25f3cf9-5959-4069-9c26-f4a1a6d0af06 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2704928349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2704928349 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/3.kmac_test_vectors_sha3_256.4159163225 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 35594464743 ps |
| CPU time | 1346.39 seconds |
| Started | May 26 02:54:57 PM PDT 24 |
| Finished | May 26 03:17:26 PM PDT 24 |
| Peak memory | 367592 kb |
| Host | smart-eb4320c9-f012-4e56-a34d-1d5ce7b2db40 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4159163225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.4159163225 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3490149973 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 14227053585 ps |
| CPU time | 1178.94 seconds |
| Started | May 26 02:54:59 PM PDT 24 |
| Finished | May 26 03:14:41 PM PDT 24 |
| Peak memory | 338088 kb |
| Host | smart-88802ee3-496e-4647-9429-eb7adbd5f59b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3490149973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3490149973 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/3.kmac_test_vectors_sha3_512.2505449290 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 36754450675 ps |
| CPU time | 815.29 seconds |
| Started | May 26 02:55:04 PM PDT 24 |
| Finished | May 26 03:08:42 PM PDT 24 |
| Peak memory | 296188 kb |
| Host | smart-a6eee492-268a-4f39-8926-7f9b233e0995 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2505449290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2505449290 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/3.kmac_test_vectors_shake_128.7580068 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 396921752499 ps |
| CPU time | 4356.2 seconds |
| Started | May 26 02:55:09 PM PDT 24 |
| Finished | May 26 04:07:47 PM PDT 24 |
| Peak memory | 665520 kb |
| Host | smart-60e914a3-7f87-4845-8435-a965355f200d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=7580068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.7580068 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/3.kmac_test_vectors_shake_256.2510288750 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 182053718930 ps |
| CPU time | 3596.48 seconds |
| Started | May 26 02:55:06 PM PDT 24 |
| Finished | May 26 03:55:05 PM PDT 24 |
| Peak memory | 571576 kb |
| Host | smart-fb909c43-852c-4efb-a1dd-aa534444bb56 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2510288750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2510288750 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/30.kmac_alert_test.2727028210 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 65372111 ps |
| CPU time | 0.79 seconds |
| Started | May 26 02:57:59 PM PDT 24 |
| Finished | May 26 02:58:00 PM PDT 24 |
| Peak memory | 204872 kb |
| Host | smart-5ef2f019-9097-4f52-b8b3-fd78d74fa475 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727028210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2727028210 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/30.kmac_app.896784049 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 12108204726 ps |
| CPU time | 146.89 seconds |
| Started | May 26 02:57:48 PM PDT 24 |
| Finished | May 26 03:00:16 PM PDT 24 |
| Peak memory | 232040 kb |
| Host | smart-47c28499-1cf1-4249-8c32-0d14d3a721d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=896784049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.896784049 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_app/latest |
| Test location | /workspace/coverage/default/30.kmac_burst_write.561984914 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 21501827658 ps |
| CPU time | 541.7 seconds |
| Started | May 26 02:57:41 PM PDT 24 |
| Finished | May 26 03:06:44 PM PDT 24 |
| Peak memory | 230188 kb |
| Host | smart-9039f644-4792-4e76-913e-f62565fd2f3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561984914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.561984914 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/30.kmac_entropy_refresh.2385771307 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 32989349491 ps |
| CPU time | 328.59 seconds |
| Started | May 26 02:57:46 PM PDT 24 |
| Finished | May 26 03:03:15 PM PDT 24 |
| Peak memory | 244864 kb |
| Host | smart-f661c7fa-ccaf-4536-a39b-2a80b44f2ec7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385771307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2385771307 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/30.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/30.kmac_error.3208154242 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 26854513142 ps |
| CPU time | 287.57 seconds |
| Started | May 26 02:57:49 PM PDT 24 |
| Finished | May 26 03:02:37 PM PDT 24 |
| Peak memory | 253888 kb |
| Host | smart-2010874a-633f-4242-8ebd-4d152715e41b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208154242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3208154242 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_error/latest |
| Test location | /workspace/coverage/default/30.kmac_key_error.379233141 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1892911820 ps |
| CPU time | 9.07 seconds |
| Started | May 26 02:57:48 PM PDT 24 |
| Finished | May 26 02:57:58 PM PDT 24 |
| Peak memory | 207156 kb |
| Host | smart-d7934c62-9da4-4ab8-984b-14d8eadcf49e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=379233141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.379233141 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_key_error/latest |
| Test location | /workspace/coverage/default/30.kmac_lc_escalation.536012735 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 80716312 ps |
| CPU time | 1.44 seconds |
| Started | May 26 02:57:48 PM PDT 24 |
| Finished | May 26 02:57:51 PM PDT 24 |
| Peak memory | 215308 kb |
| Host | smart-5edb320a-6e76-4c23-8cf8-e98fd2b1a473 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536012735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.536012735 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/30.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/30.kmac_long_msg_and_output.3083867224 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1000496660 ps |
| CPU time | 81.92 seconds |
| Started | May 26 02:57:39 PM PDT 24 |
| Finished | May 26 02:59:02 PM PDT 24 |
| Peak memory | 231200 kb |
| Host | smart-345f1709-2aab-44b5-9e32-472ce9e3d86b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083867224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a nd_output.3083867224 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/30.kmac_sideload.3087732221 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 3301481967 ps |
| CPU time | 267.84 seconds |
| Started | May 26 02:57:40 PM PDT 24 |
| Finished | May 26 03:02:08 PM PDT 24 |
| Peak memory | 242468 kb |
| Host | smart-9658ed2f-943d-4d8a-80f4-abd37dec3d51 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087732221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3087732221 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_sideload/latest |
| Test location | /workspace/coverage/default/30.kmac_smoke.473220855 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2549329159 ps |
| CPU time | 33.85 seconds |
| Started | May 26 02:57:40 PM PDT 24 |
| Finished | May 26 02:58:15 PM PDT 24 |
| Peak memory | 218544 kb |
| Host | smart-80efbfef-ee71-4377-9fb6-d8844a473ad6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473220855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.473220855 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_smoke/latest |
| Test location | /workspace/coverage/default/30.kmac_stress_all.768103981 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 19197088407 ps |
| CPU time | 46.87 seconds |
| Started | May 26 02:57:47 PM PDT 24 |
| Finished | May 26 02:58:35 PM PDT 24 |
| Peak memory | 223748 kb |
| Host | smart-6c11c049-5eb2-49b6-9e75-3f7ac61a7a6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=768103981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.768103981 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/30.kmac_test_vectors_kmac.3612298593 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 258495150 ps |
| CPU time | 4.45 seconds |
| Started | May 26 02:57:48 PM PDT 24 |
| Finished | May 26 02:57:54 PM PDT 24 |
| Peak memory | 215520 kb |
| Host | smart-35114539-0db6-4ad9-a5ac-915472bbbfb3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612298593 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.kmac_test_vectors_kmac.3612298593 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.1110482165 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 676186033 ps |
| CPU time | 4.63 seconds |
| Started | May 26 02:57:47 PM PDT 24 |
| Finished | May 26 02:57:52 PM PDT 24 |
| Peak memory | 215532 kb |
| Host | smart-65893bb5-213f-470a-969e-911824e604c3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110482165 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.1110482165 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/30.kmac_test_vectors_sha3_224.2721212307 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 68071875389 ps |
| CPU time | 1799.45 seconds |
| Started | May 26 02:57:41 PM PDT 24 |
| Finished | May 26 03:27:42 PM PDT 24 |
| Peak memory | 394300 kb |
| Host | smart-47ca1cbf-75fa-4194-9139-fe3a13c2f60a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2721212307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2721212307 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/30.kmac_test_vectors_sha3_256.2290401635 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 191482647268 ps |
| CPU time | 1877.11 seconds |
| Started | May 26 02:57:46 PM PDT 24 |
| Finished | May 26 03:29:04 PM PDT 24 |
| Peak memory | 375084 kb |
| Host | smart-0bd4b207-c2d4-4fa1-8bf4-7070a471c684 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2290401635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2290401635 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/30.kmac_test_vectors_sha3_384.61339040 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 98151496138 ps |
| CPU time | 1269.72 seconds |
| Started | May 26 02:57:48 PM PDT 24 |
| Finished | May 26 03:18:59 PM PDT 24 |
| Peak memory | 335744 kb |
| Host | smart-a8acc276-3526-4565-8492-391d84cf1ec0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=61339040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.61339040 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/30.kmac_test_vectors_sha3_512.1853402696 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 126530047684 ps |
| CPU time | 1007.1 seconds |
| Started | May 26 02:57:47 PM PDT 24 |
| Finished | May 26 03:14:35 PM PDT 24 |
| Peak memory | 296856 kb |
| Host | smart-4f964847-6758-4e30-a150-160aa2386223 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1853402696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.1853402696 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/30.kmac_test_vectors_shake_128.3236726005 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1420709993831 ps |
| CPU time | 5137.1 seconds |
| Started | May 26 02:57:47 PM PDT 24 |
| Finished | May 26 04:23:26 PM PDT 24 |
| Peak memory | 642476 kb |
| Host | smart-a7ce5fbd-7a23-408e-b681-08f64fcc2283 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3236726005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.3236726005 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/30.kmac_test_vectors_shake_256.3958534239 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 44952520252 ps |
| CPU time | 3702.58 seconds |
| Started | May 26 02:57:47 PM PDT 24 |
| Finished | May 26 03:59:31 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-fc1439dd-5b26-4081-96b5-33726f25a2fe |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3958534239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3958534239 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/30.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/31.kmac_alert_test.1968598863 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 12177056 ps |
| CPU time | 0.74 seconds |
| Started | May 26 02:58:08 PM PDT 24 |
| Finished | May 26 02:58:10 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-cd61bbfd-0a50-404d-b894-1abe949f66cd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968598863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1968598863 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/31.kmac_app.1767532460 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 19774884796 ps |
| CPU time | 246.28 seconds |
| Started | May 26 02:58:01 PM PDT 24 |
| Finished | May 26 03:02:08 PM PDT 24 |
| Peak memory | 244756 kb |
| Host | smart-4754dfbf-3dc7-4654-9242-50741646f0c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767532460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1767532460 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_app/latest |
| Test location | /workspace/coverage/default/31.kmac_burst_write.1303548617 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5385867171 ps |
| CPU time | 453.34 seconds |
| Started | May 26 02:57:59 PM PDT 24 |
| Finished | May 26 03:05:34 PM PDT 24 |
| Peak memory | 228464 kb |
| Host | smart-84932e85-e5d5-4fe1-8120-b400ef7ab312 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303548617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1303548617 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/31.kmac_entropy_refresh.1883603803 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 11258901362 ps |
| CPU time | 126.55 seconds |
| Started | May 26 02:58:08 PM PDT 24 |
| Finished | May 26 03:00:16 PM PDT 24 |
| Peak memory | 233504 kb |
| Host | smart-d6f0b964-ba1a-47bb-a67e-9767f7e65a7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883603803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1883603803 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/31.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/31.kmac_error.3186830650 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3462801203 ps |
| CPU time | 246.59 seconds |
| Started | May 26 02:58:07 PM PDT 24 |
| Finished | May 26 03:02:14 PM PDT 24 |
| Peak memory | 253648 kb |
| Host | smart-47d60ca4-e661-4c03-aa46-8a0a0489ed1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186830650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3186830650 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_error/latest |
| Test location | /workspace/coverage/default/31.kmac_key_error.1707819761 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3501438793 ps |
| CPU time | 5.28 seconds |
| Started | May 26 02:58:11 PM PDT 24 |
| Finished | May 26 02:58:17 PM PDT 24 |
| Peak memory | 215356 kb |
| Host | smart-2b974cdd-fd36-481c-b2ce-f1c114a9e0ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707819761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1707819761 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_key_error/latest |
| Test location | /workspace/coverage/default/31.kmac_lc_escalation.2852601671 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 44587788 ps |
| CPU time | 1.27 seconds |
| Started | May 26 02:58:07 PM PDT 24 |
| Finished | May 26 02:58:09 PM PDT 24 |
| Peak memory | 220252 kb |
| Host | smart-df3fbb9e-5b90-451b-8718-8a29acaa81f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852601671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2852601671 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/31.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/31.kmac_long_msg_and_output.2204588504 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 59175729570 ps |
| CPU time | 1330.89 seconds |
| Started | May 26 02:57:58 PM PDT 24 |
| Finished | May 26 03:20:10 PM PDT 24 |
| Peak memory | 328784 kb |
| Host | smart-6d85f7ed-f99f-4d69-a486-88d54e93db60 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204588504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a nd_output.2204588504 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/31.kmac_sideload.2547486310 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 11987373319 ps |
| CPU time | 332.34 seconds |
| Started | May 26 02:58:00 PM PDT 24 |
| Finished | May 26 03:03:33 PM PDT 24 |
| Peak memory | 245892 kb |
| Host | smart-e80a10e0-ea6f-4551-94e4-75fb120be431 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547486310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2547486310 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_sideload/latest |
| Test location | /workspace/coverage/default/31.kmac_smoke.949353892 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 10803152750 ps |
| CPU time | 34.59 seconds |
| Started | May 26 02:57:58 PM PDT 24 |
| Finished | May 26 02:58:33 PM PDT 24 |
| Peak memory | 216708 kb |
| Host | smart-30c47472-53ac-42f1-a756-2a398a87c605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949353892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.949353892 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_smoke/latest |
| Test location | /workspace/coverage/default/31.kmac_stress_all.174817684 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 9966939652 ps |
| CPU time | 534.46 seconds |
| Started | May 26 02:58:09 PM PDT 24 |
| Finished | May 26 03:07:04 PM PDT 24 |
| Peak memory | 308412 kb |
| Host | smart-a7074762-16e4-4880-8626-6ff4d6cbdc4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=174817684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.174817684 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/31.kmac_test_vectors_kmac.3236910314 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2117192872 ps |
| CPU time | 4.77 seconds |
| Started | May 26 02:57:57 PM PDT 24 |
| Finished | May 26 02:58:03 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-3f5ff6a9-5a3a-495d-9cda-6652210242a8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236910314 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.kmac_test_vectors_kmac.3236910314 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.230421131 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 904457846 ps |
| CPU time | 4.91 seconds |
| Started | May 26 02:57:59 PM PDT 24 |
| Finished | May 26 02:58:04 PM PDT 24 |
| Peak memory | 215552 kb |
| Host | smart-34a1dbc3-a09f-4b79-ace5-ffbcf3396ea8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230421131 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 31.kmac_test_vectors_kmac_xof.230421131 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/31.kmac_test_vectors_sha3_224.2899018973 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 67674762086 ps |
| CPU time | 1766.4 seconds |
| Started | May 26 02:57:57 PM PDT 24 |
| Finished | May 26 03:27:24 PM PDT 24 |
| Peak memory | 392452 kb |
| Host | smart-c49f1dc9-eb40-464f-8841-9fdf1ec16720 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2899018973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.2899018973 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/31.kmac_test_vectors_sha3_256.1672155427 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 251105554982 ps |
| CPU time | 1903.81 seconds |
| Started | May 26 02:57:59 PM PDT 24 |
| Finished | May 26 03:29:44 PM PDT 24 |
| Peak memory | 369096 kb |
| Host | smart-05b80219-b932-4c58-af4b-0474d286abb4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1672155427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.1672155427 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/31.kmac_test_vectors_sha3_384.2318082035 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 48198870225 ps |
| CPU time | 1370.96 seconds |
| Started | May 26 02:57:59 PM PDT 24 |
| Finished | May 26 03:20:51 PM PDT 24 |
| Peak memory | 331020 kb |
| Host | smart-ca63e7ed-dbfa-4ff8-a0aa-8e7b5d552da1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2318082035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2318082035 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1688581928 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 324389040886 ps |
| CPU time | 1006.78 seconds |
| Started | May 26 02:58:01 PM PDT 24 |
| Finished | May 26 03:14:48 PM PDT 24 |
| Peak memory | 293208 kb |
| Host | smart-803ef0d4-d61e-492d-a612-c74a2a953106 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1688581928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1688581928 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/31.kmac_test_vectors_shake_128.1764847000 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1061496233536 ps |
| CPU time | 5474.89 seconds |
| Started | May 26 02:57:58 PM PDT 24 |
| Finished | May 26 04:29:15 PM PDT 24 |
| Peak memory | 642376 kb |
| Host | smart-e36f5028-40e2-4a14-8d74-ce5f85a9b088 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1764847000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1764847000 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/31.kmac_test_vectors_shake_256.3081721855 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 150746496053 ps |
| CPU time | 4206.24 seconds |
| Started | May 26 02:57:59 PM PDT 24 |
| Finished | May 26 04:08:07 PM PDT 24 |
| Peak memory | 558244 kb |
| Host | smart-34d163ba-89ed-4de1-beea-d74bfb4c1369 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3081721855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3081721855 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/31.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/32.kmac_alert_test.3888208451 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 17602485 ps |
| CPU time | 0.81 seconds |
| Started | May 26 02:58:31 PM PDT 24 |
| Finished | May 26 02:58:33 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-a7d22912-20ae-41a4-9919-964d4c1290ad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888208451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3888208451 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/32.kmac_app.2159866037 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5355515379 ps |
| CPU time | 116.35 seconds |
| Started | May 26 02:58:14 PM PDT 24 |
| Finished | May 26 03:00:11 PM PDT 24 |
| Peak memory | 231868 kb |
| Host | smart-a9ff5bfe-a26a-49b6-8c15-f4bf2b3ae89a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159866037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2159866037 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_app/latest |
| Test location | /workspace/coverage/default/32.kmac_burst_write.1118619559 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 18545133163 ps |
| CPU time | 571.46 seconds |
| Started | May 26 02:58:08 PM PDT 24 |
| Finished | May 26 03:07:40 PM PDT 24 |
| Peak memory | 240080 kb |
| Host | smart-4129318e-66fa-4d2a-a001-04b18ceceb23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118619559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1118619559 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/32.kmac_entropy_refresh.1039158480 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1433265113 ps |
| CPU time | 58.41 seconds |
| Started | May 26 02:58:17 PM PDT 24 |
| Finished | May 26 02:59:16 PM PDT 24 |
| Peak memory | 223992 kb |
| Host | smart-37137d5e-faea-42af-8db0-b9d9ea6b786c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039158480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1039158480 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/32.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/32.kmac_error.3756233250 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4301199449 ps |
| CPU time | 88.8 seconds |
| Started | May 26 02:58:15 PM PDT 24 |
| Finished | May 26 02:59:45 PM PDT 24 |
| Peak memory | 237316 kb |
| Host | smart-ca4367aa-b441-4cda-95a8-80db9d109eee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756233250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3756233250 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_error/latest |
| Test location | /workspace/coverage/default/32.kmac_key_error.4114877073 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3840592617 ps |
| CPU time | 6.97 seconds |
| Started | May 26 02:58:15 PM PDT 24 |
| Finished | May 26 02:58:23 PM PDT 24 |
| Peak memory | 207232 kb |
| Host | smart-72b92f04-43f4-4b39-ad43-0bb1a69c20bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114877073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.4114877073 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_key_error/latest |
| Test location | /workspace/coverage/default/32.kmac_lc_escalation.2055966830 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 71194943 ps |
| CPU time | 1.27 seconds |
| Started | May 26 02:58:15 PM PDT 24 |
| Finished | May 26 02:58:17 PM PDT 24 |
| Peak memory | 216272 kb |
| Host | smart-5f247b6b-6c4d-4e42-8c9f-ed039c7554ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055966830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2055966830 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/32.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/32.kmac_long_msg_and_output.214846558 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 26049104609 ps |
| CPU time | 438.01 seconds |
| Started | May 26 02:58:08 PM PDT 24 |
| Finished | May 26 03:05:27 PM PDT 24 |
| Peak memory | 259000 kb |
| Host | smart-73b3cac0-4d94-4383-88fe-4cb88e00b8d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214846558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_an d_output.214846558 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/32.kmac_sideload.2764511582 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 107874021294 ps |
| CPU time | 204.49 seconds |
| Started | May 26 02:58:08 PM PDT 24 |
| Finished | May 26 03:01:33 PM PDT 24 |
| Peak memory | 235264 kb |
| Host | smart-b9be83f5-1980-4398-8e38-a28845dbc8f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764511582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2764511582 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_sideload/latest |
| Test location | /workspace/coverage/default/32.kmac_smoke.3437969236 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 30042228605 ps |
| CPU time | 50.69 seconds |
| Started | May 26 02:58:08 PM PDT 24 |
| Finished | May 26 02:59:00 PM PDT 24 |
| Peak memory | 220304 kb |
| Host | smart-8fd9f7fa-b412-4e95-930b-01ad990eaef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437969236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3437969236 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_smoke/latest |
| Test location | /workspace/coverage/default/32.kmac_test_vectors_kmac.906750 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 224345704 ps |
| CPU time | 4.52 seconds |
| Started | May 26 02:58:11 PM PDT 24 |
| Finished | May 26 02:58:17 PM PDT 24 |
| Peak memory | 215516 kb |
| Host | smart-d8af4e65-2afe-49e9-aae3-e49849f4cd93 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906750 -assert nopostproc +UVM_TESTNAME=kmac_base_tes t +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 32.kmac_test_vectors_kmac.906750 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2422995825 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 180099969 ps |
| CPU time | 4.85 seconds |
| Started | May 26 02:58:07 PM PDT 24 |
| Finished | May 26 02:58:13 PM PDT 24 |
| Peak memory | 215480 kb |
| Host | smart-f0c90294-d6b9-4627-8fd3-a1c15ff09ee5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422995825 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2422995825 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/32.kmac_test_vectors_sha3_224.689795979 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 126686954551 ps |
| CPU time | 1540.62 seconds |
| Started | May 26 02:58:07 PM PDT 24 |
| Finished | May 26 03:23:48 PM PDT 24 |
| Peak memory | 395996 kb |
| Host | smart-ca65e79f-eb52-4cb1-a6ff-e2b941ba85ba |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=689795979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.689795979 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/32.kmac_test_vectors_sha3_256.2368950428 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 255103736621 ps |
| CPU time | 1619.94 seconds |
| Started | May 26 02:58:07 PM PDT 24 |
| Finished | May 26 03:25:09 PM PDT 24 |
| Peak memory | 373864 kb |
| Host | smart-fb354f55-d948-492c-9807-51dd9177a940 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2368950428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2368950428 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/32.kmac_test_vectors_sha3_384.2877908758 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 53046986104 ps |
| CPU time | 1138.67 seconds |
| Started | May 26 02:58:07 PM PDT 24 |
| Finished | May 26 03:17:06 PM PDT 24 |
| Peak memory | 327616 kb |
| Host | smart-45547622-b6a3-4a4f-a1f8-c003b5e3138f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2877908758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2877908758 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/32.kmac_test_vectors_sha3_512.3809665025 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 94971173889 ps |
| CPU time | 807.54 seconds |
| Started | May 26 02:58:07 PM PDT 24 |
| Finished | May 26 03:11:36 PM PDT 24 |
| Peak memory | 293988 kb |
| Host | smart-61a031f5-7173-41ff-be28-0547a2625e7e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3809665025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3809665025 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/32.kmac_test_vectors_shake_128.2232696420 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3157989859123 ps |
| CPU time | 5670.8 seconds |
| Started | May 26 02:58:09 PM PDT 24 |
| Finished | May 26 04:32:41 PM PDT 24 |
| Peak memory | 634740 kb |
| Host | smart-9556d845-163d-47a5-9e7d-8636e88f8711 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2232696420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.2232696420 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/32.kmac_test_vectors_shake_256.1922897884 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 389504801270 ps |
| CPU time | 4389.58 seconds |
| Started | May 26 02:58:07 PM PDT 24 |
| Finished | May 26 04:11:18 PM PDT 24 |
| Peak memory | 556744 kb |
| Host | smart-607a9925-628f-43cb-9b14-6956e0189cb9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1922897884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1922897884 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/32.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/33.kmac_alert_test.917248714 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 111582043 ps |
| CPU time | 0.79 seconds |
| Started | May 26 02:58:32 PM PDT 24 |
| Finished | May 26 02:58:34 PM PDT 24 |
| Peak memory | 204872 kb |
| Host | smart-6e63e50f-f379-4a9c-9f0c-fde59be154ee |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917248714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.917248714 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/33.kmac_app.3923194422 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 9751961976 ps |
| CPU time | 102.44 seconds |
| Started | May 26 02:58:29 PM PDT 24 |
| Finished | May 26 03:00:13 PM PDT 24 |
| Peak memory | 230344 kb |
| Host | smart-e990fe0b-7a4f-4236-9af6-646cc89e9d70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3923194422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3923194422 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_app/latest |
| Test location | /workspace/coverage/default/33.kmac_burst_write.2079500586 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 7748717678 ps |
| CPU time | 226.18 seconds |
| Started | May 26 02:58:22 PM PDT 24 |
| Finished | May 26 03:02:10 PM PDT 24 |
| Peak memory | 225868 kb |
| Host | smart-649c715e-fb1c-43a3-92ed-7c71b1ac2476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079500586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2079500586 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/33.kmac_entropy_refresh.1515966799 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 20351552976 ps |
| CPU time | 260.1 seconds |
| Started | May 26 02:58:31 PM PDT 24 |
| Finished | May 26 03:02:52 PM PDT 24 |
| Peak memory | 243808 kb |
| Host | smart-f8a9aa25-5ded-4a80-81b8-dc3e5b5c3dbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1515966799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1515966799 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/33.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/33.kmac_error.702459058 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 19860534009 ps |
| CPU time | 392.1 seconds |
| Started | May 26 02:58:29 PM PDT 24 |
| Finished | May 26 03:05:02 PM PDT 24 |
| Peak memory | 256508 kb |
| Host | smart-2ab229c7-afee-48cc-a128-3941c93be98d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=702459058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.702459058 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_error/latest |
| Test location | /workspace/coverage/default/33.kmac_key_error.3987492004 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 677934729 ps |
| CPU time | 3.87 seconds |
| Started | May 26 02:58:35 PM PDT 24 |
| Finished | May 26 02:58:40 PM PDT 24 |
| Peak memory | 207100 kb |
| Host | smart-d4c76d5d-33ed-4029-adfd-20d768e1327e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987492004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3987492004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_key_error/latest |
| Test location | /workspace/coverage/default/33.kmac_long_msg_and_output.1407889350 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 76267950854 ps |
| CPU time | 2325.1 seconds |
| Started | May 26 02:58:16 PM PDT 24 |
| Finished | May 26 03:37:02 PM PDT 24 |
| Peak memory | 442988 kb |
| Host | smart-efcf6f61-3cb2-4a1a-a88b-5372e9da41f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407889350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a nd_output.1407889350 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/33.kmac_sideload.1003978672 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1673184477 ps |
| CPU time | 67.18 seconds |
| Started | May 26 02:58:15 PM PDT 24 |
| Finished | May 26 02:59:23 PM PDT 24 |
| Peak memory | 225768 kb |
| Host | smart-4b1146ee-37ba-4e9b-8dbd-e1040887b1da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003978672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1003978672 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_sideload/latest |
| Test location | /workspace/coverage/default/33.kmac_smoke.319746670 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1593823874 ps |
| CPU time | 26.02 seconds |
| Started | May 26 02:58:14 PM PDT 24 |
| Finished | May 26 02:58:41 PM PDT 24 |
| Peak memory | 218948 kb |
| Host | smart-342ee4d0-a7ba-4219-99ba-2481ca212acc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319746670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.319746670 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_smoke/latest |
| Test location | /workspace/coverage/default/33.kmac_stress_all.1967619038 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 51210657266 ps |
| CPU time | 568.73 seconds |
| Started | May 26 02:58:29 PM PDT 24 |
| Finished | May 26 03:07:59 PM PDT 24 |
| Peak memory | 315304 kb |
| Host | smart-991dd6b6-f71e-4fff-b420-a0e807ef0a1c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1967619038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1967619038 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/33.kmac_test_vectors_kmac.1257358932 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 222334471 ps |
| CPU time | 4.63 seconds |
| Started | May 26 02:58:21 PM PDT 24 |
| Finished | May 26 02:58:26 PM PDT 24 |
| Peak memory | 215532 kb |
| Host | smart-46152735-72f5-4f5c-b9f2-e71bb595f4cd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257358932 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.kmac_test_vectors_kmac.1257358932 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.1583902930 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 261244379 ps |
| CPU time | 5.29 seconds |
| Started | May 26 02:58:21 PM PDT 24 |
| Finished | May 26 02:58:27 PM PDT 24 |
| Peak memory | 215540 kb |
| Host | smart-e6922bc8-069e-4533-b5e4-a8f270d7921d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583902930 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.1583902930 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/33.kmac_test_vectors_sha3_224.1008910433 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 65600527517 ps |
| CPU time | 1799.85 seconds |
| Started | May 26 02:58:21 PM PDT 24 |
| Finished | May 26 03:28:22 PM PDT 24 |
| Peak memory | 394428 kb |
| Host | smart-f5f8156f-dcb3-4b36-a903-52d433b3b1bf |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1008910433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1008910433 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/33.kmac_test_vectors_sha3_256.2131458808 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 59622582441 ps |
| CPU time | 1665.05 seconds |
| Started | May 26 02:58:22 PM PDT 24 |
| Finished | May 26 03:26:09 PM PDT 24 |
| Peak memory | 364588 kb |
| Host | smart-d0835689-018a-4863-a369-07d3293ccc68 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2131458808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2131458808 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/33.kmac_test_vectors_sha3_384.138910805 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 61708408690 ps |
| CPU time | 1340.19 seconds |
| Started | May 26 02:58:21 PM PDT 24 |
| Finished | May 26 03:20:42 PM PDT 24 |
| Peak memory | 335052 kb |
| Host | smart-35393200-d64b-4013-a625-4d1f11abdc6c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=138910805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.138910805 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/33.kmac_test_vectors_sha3_512.2096670649 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 43314143028 ps |
| CPU time | 897.03 seconds |
| Started | May 26 02:58:21 PM PDT 24 |
| Finished | May 26 03:13:20 PM PDT 24 |
| Peak memory | 291404 kb |
| Host | smart-4d02d0db-ae26-47b7-aa19-10ab4ac8387b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2096670649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.2096670649 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/33.kmac_test_vectors_shake_128.2934214906 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 344245480147 ps |
| CPU time | 5121.75 seconds |
| Started | May 26 02:58:24 PM PDT 24 |
| Finished | May 26 04:23:47 PM PDT 24 |
| Peak memory | 652144 kb |
| Host | smart-ddbae0a5-8b93-4397-b601-cb84001004ac |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2934214906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.2934214906 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/33.kmac_test_vectors_shake_256.2018215442 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 175374961546 ps |
| CPU time | 3657.27 seconds |
| Started | May 26 02:58:21 PM PDT 24 |
| Finished | May 26 03:59:20 PM PDT 24 |
| Peak memory | 572372 kb |
| Host | smart-fddc3f01-8181-4548-9275-c61eee6b1947 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2018215442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2018215442 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/33.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/34.kmac_alert_test.496085564 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 22479294 ps |
| CPU time | 0.85 seconds |
| Started | May 26 02:58:44 PM PDT 24 |
| Finished | May 26 02:58:45 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-ac9110ba-de85-4cf8-aa5f-364898266fd5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496085564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.496085564 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/34.kmac_app.1361549439 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 48073802602 ps |
| CPU time | 191.39 seconds |
| Started | May 26 02:58:37 PM PDT 24 |
| Finished | May 26 03:01:50 PM PDT 24 |
| Peak memory | 237688 kb |
| Host | smart-c0663c73-b27d-40af-8c15-64187f1470d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1361549439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1361549439 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_app/latest |
| Test location | /workspace/coverage/default/34.kmac_burst_write.562665617 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 160315159647 ps |
| CPU time | 531.72 seconds |
| Started | May 26 02:58:29 PM PDT 24 |
| Finished | May 26 03:07:22 PM PDT 24 |
| Peak memory | 230032 kb |
| Host | smart-e7c8ebb3-2166-431e-8394-dfc80d437843 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562665617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.562665617 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/34.kmac_error.1110686390 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 106226073316 ps |
| CPU time | 401.87 seconds |
| Started | May 26 02:58:39 PM PDT 24 |
| Finished | May 26 03:05:22 PM PDT 24 |
| Peak memory | 256504 kb |
| Host | smart-874c2ff5-22b9-49d3-afb2-976bc52e1099 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110686390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1110686390 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_error/latest |
| Test location | /workspace/coverage/default/34.kmac_key_error.2385457578 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 4989716094 ps |
| CPU time | 6.78 seconds |
| Started | May 26 02:58:37 PM PDT 24 |
| Finished | May 26 02:58:45 PM PDT 24 |
| Peak memory | 207236 kb |
| Host | smart-424b1b7d-f619-4269-b214-a760139b9178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385457578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2385457578 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_key_error/latest |
| Test location | /workspace/coverage/default/34.kmac_lc_escalation.883884826 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 117243722 ps |
| CPU time | 1.18 seconds |
| Started | May 26 02:58:39 PM PDT 24 |
| Finished | May 26 02:58:40 PM PDT 24 |
| Peak memory | 215360 kb |
| Host | smart-960ee2fe-c6b4-4992-a7ad-49c5ca0b0c27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883884826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.883884826 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/34.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/34.kmac_long_msg_and_output.2627695120 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 19108371802 ps |
| CPU time | 412.75 seconds |
| Started | May 26 02:58:28 PM PDT 24 |
| Finished | May 26 03:05:22 PM PDT 24 |
| Peak memory | 259076 kb |
| Host | smart-359a50be-36e2-43e9-80db-05977f5c2621 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627695120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a nd_output.2627695120 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/34.kmac_sideload.2272620359 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 483843107 ps |
| CPU time | 37.28 seconds |
| Started | May 26 02:58:29 PM PDT 24 |
| Finished | May 26 02:59:07 PM PDT 24 |
| Peak memory | 219880 kb |
| Host | smart-f3fe78f8-172b-44d6-8066-68afd4d48453 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272620359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2272620359 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_sideload/latest |
| Test location | /workspace/coverage/default/34.kmac_smoke.3243298048 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 7355966751 ps |
| CPU time | 40.3 seconds |
| Started | May 26 02:58:30 PM PDT 24 |
| Finished | May 26 02:59:11 PM PDT 24 |
| Peak memory | 223676 kb |
| Host | smart-42479bb4-a815-48c9-b76f-b118cd1d2276 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243298048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3243298048 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_smoke/latest |
| Test location | /workspace/coverage/default/34.kmac_stress_all.3695258816 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 4354239533 ps |
| CPU time | 99.56 seconds |
| Started | May 26 02:58:38 PM PDT 24 |
| Finished | May 26 03:00:18 PM PDT 24 |
| Peak memory | 248728 kb |
| Host | smart-61fd2206-2144-4e1c-b0b9-aad129648559 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3695258816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3695258816 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/34.kmac_test_vectors_kmac.2748040016 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3865902897 ps |
| CPU time | 6.14 seconds |
| Started | May 26 02:58:37 PM PDT 24 |
| Finished | May 26 02:58:43 PM PDT 24 |
| Peak memory | 215580 kb |
| Host | smart-3e2bcb9c-fe0e-4a12-bd50-c13cd9aec24a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748040016 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.kmac_test_vectors_kmac.2748040016 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.399022215 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 67336103 ps |
| CPU time | 4.13 seconds |
| Started | May 26 02:58:36 PM PDT 24 |
| Finished | May 26 02:58:41 PM PDT 24 |
| Peak memory | 215532 kb |
| Host | smart-5f1332ac-769e-45ae-895f-7dedda5d04d8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399022215 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 34.kmac_test_vectors_kmac_xof.399022215 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/34.kmac_test_vectors_sha3_224.4027225841 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 134055589724 ps |
| CPU time | 1702.63 seconds |
| Started | May 26 02:58:35 PM PDT 24 |
| Finished | May 26 03:26:59 PM PDT 24 |
| Peak memory | 389000 kb |
| Host | smart-f4571481-11f4-4124-a719-1d34933333a4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4027225841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.4027225841 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/34.kmac_test_vectors_sha3_256.3034042494 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 60536971827 ps |
| CPU time | 1749.33 seconds |
| Started | May 26 02:58:29 PM PDT 24 |
| Finished | May 26 03:27:40 PM PDT 24 |
| Peak memory | 371080 kb |
| Host | smart-02dac62a-4add-40e9-ac99-61bed01074af |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3034042494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.3034042494 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/34.kmac_test_vectors_sha3_384.937234388 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 59632322273 ps |
| CPU time | 1238.5 seconds |
| Started | May 26 02:58:32 PM PDT 24 |
| Finished | May 26 03:19:11 PM PDT 24 |
| Peak memory | 328544 kb |
| Host | smart-8a7b8b04-f211-49ff-95bb-f7c2dbd6d61b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=937234388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.937234388 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/34.kmac_test_vectors_sha3_512.3848002694 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 41428610653 ps |
| CPU time | 898.37 seconds |
| Started | May 26 02:58:33 PM PDT 24 |
| Finished | May 26 03:13:32 PM PDT 24 |
| Peak memory | 290580 kb |
| Host | smart-aa29129e-62a0-4141-aea1-f1fd07072c95 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3848002694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.3848002694 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/34.kmac_test_vectors_shake_128.1365801469 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 100989735017 ps |
| CPU time | 4240.21 seconds |
| Started | May 26 02:58:34 PM PDT 24 |
| Finished | May 26 04:09:15 PM PDT 24 |
| Peak memory | 663748 kb |
| Host | smart-742d1ca8-cd3e-42b5-b790-37b83ba1db56 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1365801469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.1365801469 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/34.kmac_test_vectors_shake_256.3227823858 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 149678542767 ps |
| CPU time | 4118.39 seconds |
| Started | May 26 02:58:31 PM PDT 24 |
| Finished | May 26 04:07:11 PM PDT 24 |
| Peak memory | 559688 kb |
| Host | smart-0e3b149e-ded1-4f43-a3b5-4f99d794a645 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3227823858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.3227823858 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/34.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/35.kmac_alert_test.2746466883 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 43209102 ps |
| CPU time | 0.78 seconds |
| Started | May 26 02:58:52 PM PDT 24 |
| Finished | May 26 02:58:54 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-809ccb76-dc4e-4edc-94bb-942c3cc5c212 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746466883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2746466883 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/35.kmac_app.2489765670 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 10698221275 ps |
| CPU time | 242.36 seconds |
| Started | May 26 02:58:52 PM PDT 24 |
| Finished | May 26 03:02:56 PM PDT 24 |
| Peak memory | 244464 kb |
| Host | smart-6a49e246-8882-42b2-aff1-686d33857c10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489765670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2489765670 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_app/latest |
| Test location | /workspace/coverage/default/35.kmac_burst_write.510440648 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 26779163786 ps |
| CPU time | 162.49 seconds |
| Started | May 26 02:58:45 PM PDT 24 |
| Finished | May 26 03:01:28 PM PDT 24 |
| Peak memory | 223708 kb |
| Host | smart-5d67e238-4d9c-4655-bd9d-4dd2d2f6e604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510440648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.510440648 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/35.kmac_entropy_refresh.4243757830 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 110290444199 ps |
| CPU time | 196.85 seconds |
| Started | May 26 02:58:51 PM PDT 24 |
| Finished | May 26 03:02:10 PM PDT 24 |
| Peak memory | 235980 kb |
| Host | smart-5b20134d-697b-469e-9415-626a0a8ac0dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243757830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.4243757830 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/35.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/35.kmac_error.913591622 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 36448052694 ps |
| CPU time | 373.22 seconds |
| Started | May 26 02:58:51 PM PDT 24 |
| Finished | May 26 03:05:06 PM PDT 24 |
| Peak memory | 256572 kb |
| Host | smart-73f9e4ae-3e34-4cec-ab9b-f9111831659b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913591622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.913591622 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_error/latest |
| Test location | /workspace/coverage/default/35.kmac_key_error.1015247792 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 291684056 ps |
| CPU time | 2.19 seconds |
| Started | May 26 02:58:51 PM PDT 24 |
| Finished | May 26 02:58:54 PM PDT 24 |
| Peak memory | 207252 kb |
| Host | smart-50d24fa8-66b7-4b60-a991-26c37d25fc86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015247792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1015247792 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_key_error/latest |
| Test location | /workspace/coverage/default/35.kmac_lc_escalation.3313198865 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 69740227 ps |
| CPU time | 1.18 seconds |
| Started | May 26 02:58:51 PM PDT 24 |
| Finished | May 26 02:58:54 PM PDT 24 |
| Peak memory | 215336 kb |
| Host | smart-cd4a3aee-41d1-4079-8d3f-0a085e3e46e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313198865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3313198865 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/35.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/35.kmac_long_msg_and_output.3915977519 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 59350449987 ps |
| CPU time | 1550.19 seconds |
| Started | May 26 02:58:46 PM PDT 24 |
| Finished | May 26 03:24:37 PM PDT 24 |
| Peak memory | 392956 kb |
| Host | smart-991888a2-4bc6-4076-ab0c-68ec3fe402ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915977519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a nd_output.3915977519 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/35.kmac_sideload.4015069554 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 9360710216 ps |
| CPU time | 36.33 seconds |
| Started | May 26 02:58:43 PM PDT 24 |
| Finished | May 26 02:59:20 PM PDT 24 |
| Peak memory | 223484 kb |
| Host | smart-84b77c6d-4022-49e6-b169-a3347290756d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015069554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.4015069554 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_sideload/latest |
| Test location | /workspace/coverage/default/35.kmac_smoke.2041746604 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4594967063 ps |
| CPU time | 51.31 seconds |
| Started | May 26 02:58:43 PM PDT 24 |
| Finished | May 26 02:59:35 PM PDT 24 |
| Peak memory | 216012 kb |
| Host | smart-82768007-ccda-4d19-88a5-fb44431a7a14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041746604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2041746604 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_smoke/latest |
| Test location | /workspace/coverage/default/35.kmac_stress_all.1474124729 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 47919075470 ps |
| CPU time | 1315.63 seconds |
| Started | May 26 02:58:51 PM PDT 24 |
| Finished | May 26 03:20:48 PM PDT 24 |
| Peak memory | 371628 kb |
| Host | smart-f22c0fea-3142-4d9c-a285-6c96eab0815c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1474124729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1474124729 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/35.kmac_test_vectors_kmac.1486403887 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 249049221 ps |
| CPU time | 4.16 seconds |
| Started | May 26 02:58:44 PM PDT 24 |
| Finished | May 26 02:58:49 PM PDT 24 |
| Peak memory | 215416 kb |
| Host | smart-7663736a-9e96-4c54-9be5-8540738a6e64 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486403887 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.kmac_test_vectors_kmac.1486403887 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.2849497318 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 249453215 ps |
| CPU time | 4.16 seconds |
| Started | May 26 02:58:52 PM PDT 24 |
| Finished | May 26 02:58:58 PM PDT 24 |
| Peak memory | 215532 kb |
| Host | smart-551fd278-2ae0-40a9-ba81-9a0a44e8ad5c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849497318 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac_xof.2849497318 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2656949998 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 21439133889 ps |
| CPU time | 1500.99 seconds |
| Started | May 26 02:58:46 PM PDT 24 |
| Finished | May 26 03:23:48 PM PDT 24 |
| Peak memory | 376208 kb |
| Host | smart-3483466a-d981-4f71-ac9f-62184ab42589 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2656949998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2656949998 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/35.kmac_test_vectors_sha3_256.300541093 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 30632334473 ps |
| CPU time | 1499.19 seconds |
| Started | May 26 02:58:44 PM PDT 24 |
| Finished | May 26 03:23:45 PM PDT 24 |
| Peak memory | 374592 kb |
| Host | smart-f888253f-3348-4278-b828-e7ad777961a2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=300541093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.300541093 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/35.kmac_test_vectors_sha3_384.1706218424 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 95511639738 ps |
| CPU time | 1350.12 seconds |
| Started | May 26 02:58:43 PM PDT 24 |
| Finished | May 26 03:21:14 PM PDT 24 |
| Peak memory | 339652 kb |
| Host | smart-b51a4370-b8e5-4052-9c88-63947030db0b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1706218424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.1706218424 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/35.kmac_test_vectors_sha3_512.2466490778 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 149652291765 ps |
| CPU time | 942.64 seconds |
| Started | May 26 02:58:44 PM PDT 24 |
| Finished | May 26 03:14:28 PM PDT 24 |
| Peak memory | 296452 kb |
| Host | smart-09c22113-2777-4302-ad58-7a6828b562c7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2466490778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2466490778 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/35.kmac_test_vectors_shake_128.3000020240 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 51321450830 ps |
| CPU time | 3936.69 seconds |
| Started | May 26 02:58:44 PM PDT 24 |
| Finished | May 26 04:04:21 PM PDT 24 |
| Peak memory | 648460 kb |
| Host | smart-1403a4fb-0a4f-4d0b-8e77-74ceb381e978 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3000020240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.3000020240 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/35.kmac_test_vectors_shake_256.3413582980 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 44839765021 ps |
| CPU time | 3533.14 seconds |
| Started | May 26 02:58:46 PM PDT 24 |
| Finished | May 26 03:57:40 PM PDT 24 |
| Peak memory | 556396 kb |
| Host | smart-0ee99ff3-b4f0-4c62-8448-39926cb00ea4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3413582980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.3413582980 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/35.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/36.kmac_alert_test.2402974787 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 52445073 ps |
| CPU time | 0.76 seconds |
| Started | May 26 02:59:08 PM PDT 24 |
| Finished | May 26 02:59:11 PM PDT 24 |
| Peak memory | 204872 kb |
| Host | smart-18d3de3c-78f5-43ca-ae83-4d0d8a460b0b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402974787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2402974787 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/36.kmac_burst_write.1947972231 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2199591777 ps |
| CPU time | 51.53 seconds |
| Started | May 26 02:59:02 PM PDT 24 |
| Finished | May 26 02:59:54 PM PDT 24 |
| Peak memory | 219328 kb |
| Host | smart-11fe5c99-687c-492a-b93b-a56f3e9b5895 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947972231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1947972231 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/36.kmac_entropy_refresh.2924427307 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 1244860220 ps |
| CPU time | 16.64 seconds |
| Started | May 26 02:59:05 PM PDT 24 |
| Finished | May 26 02:59:23 PM PDT 24 |
| Peak memory | 223748 kb |
| Host | smart-d37de1c8-c539-4f21-b344-ab9daed597d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924427307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2924427307 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/36.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/36.kmac_error.3702221357 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 81374362444 ps |
| CPU time | 249.13 seconds |
| Started | May 26 02:59:05 PM PDT 24 |
| Finished | May 26 03:03:15 PM PDT 24 |
| Peak memory | 249684 kb |
| Host | smart-8406c3dc-c5e7-4f91-8add-5da2319bec87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3702221357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3702221357 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_error/latest |
| Test location | /workspace/coverage/default/36.kmac_key_error.3886095736 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1167079523 ps |
| CPU time | 6.54 seconds |
| Started | May 26 02:59:06 PM PDT 24 |
| Finished | May 26 02:59:14 PM PDT 24 |
| Peak memory | 207100 kb |
| Host | smart-cb73f60f-e885-4745-a1c4-e9fd6613bf24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886095736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3886095736 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_key_error/latest |
| Test location | /workspace/coverage/default/36.kmac_lc_escalation.2984619009 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 3122366990 ps |
| CPU time | 14.92 seconds |
| Started | May 26 02:59:06 PM PDT 24 |
| Finished | May 26 02:59:22 PM PDT 24 |
| Peak memory | 226844 kb |
| Host | smart-594624ed-6925-4e08-9bfa-902768cdac37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984619009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2984619009 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/36.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/36.kmac_long_msg_and_output.2612097841 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 40852153978 ps |
| CPU time | 259.97 seconds |
| Started | May 26 02:59:00 PM PDT 24 |
| Finished | May 26 03:03:20 PM PDT 24 |
| Peak memory | 240256 kb |
| Host | smart-7e5ee906-9ea6-4713-ac7f-94555c38d22f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612097841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a nd_output.2612097841 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/36.kmac_sideload.63328849 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 910864371 ps |
| CPU time | 18.07 seconds |
| Started | May 26 02:58:59 PM PDT 24 |
| Finished | May 26 02:59:17 PM PDT 24 |
| Peak memory | 220424 kb |
| Host | smart-9e106a79-18b9-4f2e-b899-e441217aae71 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63328849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.63328849 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_sideload/latest |
| Test location | /workspace/coverage/default/36.kmac_smoke.3096775678 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 13208294335 ps |
| CPU time | 57.68 seconds |
| Started | May 26 02:58:54 PM PDT 24 |
| Finished | May 26 02:59:53 PM PDT 24 |
| Peak memory | 220448 kb |
| Host | smart-e845de72-4567-426c-b778-96d2fe2efa4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096775678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3096775678 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_smoke/latest |
| Test location | /workspace/coverage/default/36.kmac_stress_all.818835728 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 36015018891 ps |
| CPU time | 172.19 seconds |
| Started | May 26 02:59:06 PM PDT 24 |
| Finished | May 26 03:02:00 PM PDT 24 |
| Peak memory | 247908 kb |
| Host | smart-ce2eb124-964d-4698-89a0-f5429b16dcf7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=818835728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.818835728 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/36.kmac_test_vectors_kmac.784451457 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 264029650 ps |
| CPU time | 3.77 seconds |
| Started | May 26 02:59:08 PM PDT 24 |
| Finished | May 26 02:59:14 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-1ca78dba-5e82-4261-bea3-5721b3b391c5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784451457 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 36.kmac_test_vectors_kmac.784451457 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.1193225874 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 212275683 ps |
| CPU time | 4.64 seconds |
| Started | May 26 02:59:07 PM PDT 24 |
| Finished | May 26 02:59:13 PM PDT 24 |
| Peak memory | 215560 kb |
| Host | smart-cb2a0fe9-0f98-4f44-8f4d-5011608a9ef1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193225874 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac_xof.1193225874 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/36.kmac_test_vectors_sha3_224.804088862 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 279174697576 ps |
| CPU time | 1844.87 seconds |
| Started | May 26 02:59:02 PM PDT 24 |
| Finished | May 26 03:29:48 PM PDT 24 |
| Peak memory | 403852 kb |
| Host | smart-810bc057-e1a6-4d0e-989f-dc6319b0718f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=804088862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.804088862 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/36.kmac_test_vectors_sha3_256.3151039179 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 74181983452 ps |
| CPU time | 1368.04 seconds |
| Started | May 26 02:59:02 PM PDT 24 |
| Finished | May 26 03:21:51 PM PDT 24 |
| Peak memory | 375332 kb |
| Host | smart-956b6a8a-12e4-44c9-b880-8162ac44e1e7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3151039179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.3151039179 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/36.kmac_test_vectors_sha3_384.1736594453 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 72528776876 ps |
| CPU time | 1402.05 seconds |
| Started | May 26 02:59:01 PM PDT 24 |
| Finished | May 26 03:22:24 PM PDT 24 |
| Peak memory | 335472 kb |
| Host | smart-6d63d760-c029-4c90-be2c-d2155c61bf04 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1736594453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.1736594453 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/36.kmac_test_vectors_sha3_512.2072458012 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 66693619421 ps |
| CPU time | 1016.59 seconds |
| Started | May 26 02:59:07 PM PDT 24 |
| Finished | May 26 03:16:05 PM PDT 24 |
| Peak memory | 294580 kb |
| Host | smart-21f3eba2-f237-40d6-8abd-6e9cb9c8ceff |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2072458012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.2072458012 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/36.kmac_test_vectors_shake_128.3738596089 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 178275795506 ps |
| CPU time | 5093.17 seconds |
| Started | May 26 02:59:06 PM PDT 24 |
| Finished | May 26 04:24:01 PM PDT 24 |
| Peak memory | 645820 kb |
| Host | smart-06f12741-fecd-4b31-90c7-3af0cc071abd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3738596089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.3738596089 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/36.kmac_test_vectors_shake_256.2483301641 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 143676801845 ps |
| CPU time | 4006.41 seconds |
| Started | May 26 02:59:08 PM PDT 24 |
| Finished | May 26 04:05:56 PM PDT 24 |
| Peak memory | 551496 kb |
| Host | smart-608dc104-e4fc-4257-a745-df69a57d06fd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2483301641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.2483301641 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/36.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/37.kmac_alert_test.1521064719 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 16238179 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:59:23 PM PDT 24 |
| Finished | May 26 02:59:24 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-3059a75c-b5a5-4962-9a0b-34a523ed3b15 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521064719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1521064719 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/37.kmac_app.2817930414 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 39112364434 ps |
| CPU time | 298.47 seconds |
| Started | May 26 02:59:15 PM PDT 24 |
| Finished | May 26 03:04:15 PM PDT 24 |
| Peak memory | 246928 kb |
| Host | smart-5523f582-63ec-4f97-8bd9-373739f7875f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817930414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2817930414 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_app/latest |
| Test location | /workspace/coverage/default/37.kmac_burst_write.2743251490 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 20611215749 ps |
| CPU time | 121.58 seconds |
| Started | May 26 02:59:15 PM PDT 24 |
| Finished | May 26 03:01:18 PM PDT 24 |
| Peak memory | 223776 kb |
| Host | smart-0a766945-d1a1-47c4-8f53-798e06a7cd4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743251490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.2743251490 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/37.kmac_entropy_refresh.4231806902 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 12368685617 ps |
| CPU time | 153.54 seconds |
| Started | May 26 02:59:14 PM PDT 24 |
| Finished | May 26 03:01:48 PM PDT 24 |
| Peak memory | 237424 kb |
| Host | smart-30a38b42-46ab-43da-b475-abb9596acd9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231806902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.4231806902 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/37.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/37.kmac_error.4209943561 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9428389064 ps |
| CPU time | 130.73 seconds |
| Started | May 26 02:59:16 PM PDT 24 |
| Finished | May 26 03:01:28 PM PDT 24 |
| Peak memory | 248292 kb |
| Host | smart-97256f3a-3d33-4542-9859-efd65c9eddb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209943561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.4209943561 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_error/latest |
| Test location | /workspace/coverage/default/37.kmac_key_error.2445988512 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1735342926 ps |
| CPU time | 8.29 seconds |
| Started | May 26 02:59:16 PM PDT 24 |
| Finished | May 26 02:59:25 PM PDT 24 |
| Peak memory | 207164 kb |
| Host | smart-3907bebe-6626-4e63-9128-8c25096eab17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445988512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.2445988512 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_key_error/latest |
| Test location | /workspace/coverage/default/37.kmac_lc_escalation.3693336615 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 119306271 ps |
| CPU time | 1.16 seconds |
| Started | May 26 02:59:15 PM PDT 24 |
| Finished | May 26 02:59:17 PM PDT 24 |
| Peak memory | 215296 kb |
| Host | smart-98af23be-379a-403b-b2f7-729e84b3b8ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693336615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3693336615 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/37.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/37.kmac_long_msg_and_output.758585996 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 21648455611 ps |
| CPU time | 1400.91 seconds |
| Started | May 26 02:59:07 PM PDT 24 |
| Finished | May 26 03:22:29 PM PDT 24 |
| Peak memory | 371456 kb |
| Host | smart-847ab96f-dcf7-48e0-831b-9d1cb8bd30ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758585996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an d_output.758585996 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/37.kmac_sideload.1431834347 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 34997162008 ps |
| CPU time | 362.43 seconds |
| Started | May 26 02:59:07 PM PDT 24 |
| Finished | May 26 03:05:11 PM PDT 24 |
| Peak memory | 248580 kb |
| Host | smart-16f9c9b5-14f2-453f-ac2d-ec4da2fec5e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431834347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1431834347 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_sideload/latest |
| Test location | /workspace/coverage/default/37.kmac_smoke.2306802561 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2022002558 ps |
| CPU time | 43.43 seconds |
| Started | May 26 02:59:07 PM PDT 24 |
| Finished | May 26 02:59:51 PM PDT 24 |
| Peak memory | 218592 kb |
| Host | smart-3cf7d2f9-91eb-4c94-a3d9-bd44b3d802b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2306802561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2306802561 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_smoke/latest |
| Test location | /workspace/coverage/default/37.kmac_stress_all.3032902151 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 37539183603 ps |
| CPU time | 679.47 seconds |
| Started | May 26 02:59:20 PM PDT 24 |
| Finished | May 26 03:10:40 PM PDT 24 |
| Peak memory | 335468 kb |
| Host | smart-7a731ce1-bc29-4eb7-8a6b-74a7cc5232ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3032902151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3032902151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/37.kmac_test_vectors_kmac.2773558982 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 221047902 ps |
| CPU time | 4.53 seconds |
| Started | May 26 02:59:14 PM PDT 24 |
| Finished | May 26 02:59:19 PM PDT 24 |
| Peak memory | 215572 kb |
| Host | smart-d3cbc6a4-4f5e-4791-b712-5f0b6a60e996 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773558982 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.kmac_test_vectors_kmac.2773558982 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.888611586 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 66512366 ps |
| CPU time | 4.15 seconds |
| Started | May 26 02:59:15 PM PDT 24 |
| Finished | May 26 02:59:21 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-828c3a33-9d00-4caa-90da-dba95a024116 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888611586 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 37.kmac_test_vectors_kmac_xof.888611586 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/37.kmac_test_vectors_sha3_224.678954106 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 419609198438 ps |
| CPU time | 1832.96 seconds |
| Started | May 26 02:59:15 PM PDT 24 |
| Finished | May 26 03:29:49 PM PDT 24 |
| Peak memory | 390704 kb |
| Host | smart-6048c7bb-ccf1-4c99-b39c-732564bca649 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=678954106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.678954106 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/37.kmac_test_vectors_sha3_256.2046694467 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 64069897856 ps |
| CPU time | 1701.97 seconds |
| Started | May 26 02:59:13 PM PDT 24 |
| Finished | May 26 03:27:36 PM PDT 24 |
| Peak memory | 386904 kb |
| Host | smart-e942a01b-2e18-4827-8322-54a3246ce3b8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2046694467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2046694467 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/37.kmac_test_vectors_sha3_384.3069523240 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 47274981896 ps |
| CPU time | 1280.85 seconds |
| Started | May 26 02:59:15 PM PDT 24 |
| Finished | May 26 03:20:37 PM PDT 24 |
| Peak memory | 328856 kb |
| Host | smart-297152c7-0ed6-498a-beef-7915f6caa6e5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3069523240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3069523240 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/37.kmac_test_vectors_sha3_512.919177004 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 47612164575 ps |
| CPU time | 993.15 seconds |
| Started | May 26 02:59:15 PM PDT 24 |
| Finished | May 26 03:15:50 PM PDT 24 |
| Peak memory | 297432 kb |
| Host | smart-c86da6d4-2f9b-40f6-9bf7-7ec28830b062 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=919177004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.919177004 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/37.kmac_test_vectors_shake_128.3200664675 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 199580860715 ps |
| CPU time | 4166.23 seconds |
| Started | May 26 02:59:15 PM PDT 24 |
| Finished | May 26 04:08:42 PM PDT 24 |
| Peak memory | 630592 kb |
| Host | smart-b9a3f682-e471-4ea1-a334-48036a1898a4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3200664675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.3200664675 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/37.kmac_test_vectors_shake_256.1908150758 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 612684545410 ps |
| CPU time | 4156.84 seconds |
| Started | May 26 02:59:16 PM PDT 24 |
| Finished | May 26 04:08:34 PM PDT 24 |
| Peak memory | 569592 kb |
| Host | smart-b26ecffc-b064-41cb-913a-6bdd3ba9cb11 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1908150758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.1908150758 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/37.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/38.kmac_alert_test.3358961965 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 60705230 ps |
| CPU time | 0.79 seconds |
| Started | May 26 02:59:32 PM PDT 24 |
| Finished | May 26 02:59:33 PM PDT 24 |
| Peak memory | 204872 kb |
| Host | smart-d7ea6ea7-91ef-4176-a100-ad5d45c34864 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358961965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3358961965 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/38.kmac_app.4015501480 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 8035237452 ps |
| CPU time | 270.45 seconds |
| Started | May 26 02:59:29 PM PDT 24 |
| Finished | May 26 03:04:01 PM PDT 24 |
| Peak memory | 244284 kb |
| Host | smart-5008b861-577a-4ef0-89ec-780d528b7041 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015501480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.4015501480 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_app/latest |
| Test location | /workspace/coverage/default/38.kmac_burst_write.586695403 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 19483801954 ps |
| CPU time | 447.76 seconds |
| Started | May 26 02:59:22 PM PDT 24 |
| Finished | May 26 03:06:50 PM PDT 24 |
| Peak memory | 229008 kb |
| Host | smart-f3afa7f6-50ad-472f-8656-6ec71b985cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586695403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.586695403 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/38.kmac_entropy_refresh.1267145403 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2064700022 ps |
| CPU time | 40.17 seconds |
| Started | May 26 02:59:29 PM PDT 24 |
| Finished | May 26 03:00:10 PM PDT 24 |
| Peak memory | 223716 kb |
| Host | smart-2a2e6813-735f-4c4e-9bff-a3c7841d07b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1267145403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1267145403 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/38.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/38.kmac_error.992306426 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4793534610 ps |
| CPU time | 162.51 seconds |
| Started | May 26 02:59:28 PM PDT 24 |
| Finished | May 26 03:02:11 PM PDT 24 |
| Peak memory | 253344 kb |
| Host | smart-aa77c595-9e2d-4925-aece-6b8446ce1773 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992306426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.992306426 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_error/latest |
| Test location | /workspace/coverage/default/38.kmac_key_error.653733344 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 230480406 ps |
| CPU time | 1.74 seconds |
| Started | May 26 02:59:30 PM PDT 24 |
| Finished | May 26 02:59:32 PM PDT 24 |
| Peak memory | 206976 kb |
| Host | smart-538e9a49-516a-4641-82b3-9f29c587559a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653733344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.653733344 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_key_error/latest |
| Test location | /workspace/coverage/default/38.kmac_lc_escalation.3239598080 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 80573835 ps |
| CPU time | 1.22 seconds |
| Started | May 26 02:59:30 PM PDT 24 |
| Finished | May 26 02:59:32 PM PDT 24 |
| Peak memory | 215376 kb |
| Host | smart-bbea8c2f-de98-4d3d-9428-1b411ec1c825 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239598080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3239598080 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/38.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/38.kmac_long_msg_and_output.3433339511 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 88279387457 ps |
| CPU time | 2733.8 seconds |
| Started | May 26 02:59:22 PM PDT 24 |
| Finished | May 26 03:44:57 PM PDT 24 |
| Peak memory | 462264 kb |
| Host | smart-f4779e98-fb06-4079-8130-47f325c87fde |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433339511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a nd_output.3433339511 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/38.kmac_sideload.2869907377 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 43707586112 ps |
| CPU time | 436.63 seconds |
| Started | May 26 02:59:22 PM PDT 24 |
| Finished | May 26 03:06:39 PM PDT 24 |
| Peak memory | 247928 kb |
| Host | smart-c93187a7-33eb-4336-932a-676f6af86d84 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869907377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2869907377 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_sideload/latest |
| Test location | /workspace/coverage/default/38.kmac_smoke.3567107388 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3583332147 ps |
| CPU time | 44.81 seconds |
| Started | May 26 02:59:21 PM PDT 24 |
| Finished | May 26 03:00:06 PM PDT 24 |
| Peak memory | 215792 kb |
| Host | smart-6d9021d4-3c43-4cf1-a568-ed694813459a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567107388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3567107388 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_smoke/latest |
| Test location | /workspace/coverage/default/38.kmac_stress_all.266371156 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 40518617497 ps |
| CPU time | 171.58 seconds |
| Started | May 26 02:59:32 PM PDT 24 |
| Finished | May 26 03:02:24 PM PDT 24 |
| Peak memory | 255044 kb |
| Host | smart-52c5f6eb-0caa-4656-b471-51f3f055f1a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=266371156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.266371156 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/38.kmac_test_vectors_kmac.2674835764 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 68461577 ps |
| CPU time | 4.28 seconds |
| Started | May 26 02:59:29 PM PDT 24 |
| Finished | May 26 02:59:34 PM PDT 24 |
| Peak memory | 215556 kb |
| Host | smart-4e6645ce-6a80-44e5-874d-a18719ad0360 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674835764 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.kmac_test_vectors_kmac.2674835764 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.3024998040 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 68890356 ps |
| CPU time | 3.79 seconds |
| Started | May 26 02:59:30 PM PDT 24 |
| Finished | May 26 02:59:34 PM PDT 24 |
| Peak memory | 215572 kb |
| Host | smart-8728f0d8-c18e-4dcd-abe4-722c1a0ac228 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024998040 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.3024998040 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1556570376 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 102567061041 ps |
| CPU time | 1499.56 seconds |
| Started | May 26 02:59:20 PM PDT 24 |
| Finished | May 26 03:24:20 PM PDT 24 |
| Peak memory | 377680 kb |
| Host | smart-88a27a18-f5b5-496d-8b90-07d09b9a3e0d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1556570376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1556570376 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/38.kmac_test_vectors_sha3_256.1628238538 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 36693927806 ps |
| CPU time | 1358.28 seconds |
| Started | May 26 02:59:21 PM PDT 24 |
| Finished | May 26 03:22:00 PM PDT 24 |
| Peak memory | 371364 kb |
| Host | smart-d1adab2a-8079-4bd2-aa67-4af11ac53a68 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1628238538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.1628238538 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/38.kmac_test_vectors_sha3_384.1066615504 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 47150495006 ps |
| CPU time | 1262.22 seconds |
| Started | May 26 02:59:20 PM PDT 24 |
| Finished | May 26 03:20:23 PM PDT 24 |
| Peak memory | 330320 kb |
| Host | smart-15c92be7-2628-4cf2-b476-5cf3b30b424c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1066615504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1066615504 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/38.kmac_test_vectors_sha3_512.680655569 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 178643892083 ps |
| CPU time | 1071.53 seconds |
| Started | May 26 02:59:20 PM PDT 24 |
| Finished | May 26 03:17:12 PM PDT 24 |
| Peak memory | 292624 kb |
| Host | smart-7b7801d0-8d9d-4f32-b677-a568b3e8d82c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=680655569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.680655569 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/38.kmac_test_vectors_shake_128.1902062740 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 259717672857 ps |
| CPU time | 5444.38 seconds |
| Started | May 26 02:59:29 PM PDT 24 |
| Finished | May 26 04:30:15 PM PDT 24 |
| Peak memory | 641632 kb |
| Host | smart-2c2ace32-93be-4546-a78f-ddb57faa2548 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1902062740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.1902062740 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/38.kmac_test_vectors_shake_256.2813086185 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 896400634816 ps |
| CPU time | 4674.57 seconds |
| Started | May 26 02:59:28 PM PDT 24 |
| Finished | May 26 04:17:25 PM PDT 24 |
| Peak memory | 553604 kb |
| Host | smart-58cf7fa4-d324-400b-abb2-69a785a16d5e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2813086185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.2813086185 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/38.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/39.kmac_alert_test.2539973388 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 147546186 ps |
| CPU time | 0.8 seconds |
| Started | May 26 02:59:52 PM PDT 24 |
| Finished | May 26 02:59:53 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-5937fd9f-a293-44c1-a435-a5e170a1ecd5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539973388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2539973388 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/39.kmac_app.2454219976 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 16784204401 ps |
| CPU time | 103.7 seconds |
| Started | May 26 02:59:43 PM PDT 24 |
| Finished | May 26 03:01:28 PM PDT 24 |
| Peak memory | 228612 kb |
| Host | smart-e83e3dea-57cd-4ffe-8379-8922539f4078 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454219976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2454219976 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_app/latest |
| Test location | /workspace/coverage/default/39.kmac_burst_write.2422457608 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1418682007 ps |
| CPU time | 45.63 seconds |
| Started | May 26 02:59:37 PM PDT 24 |
| Finished | May 26 03:00:24 PM PDT 24 |
| Peak memory | 226492 kb |
| Host | smart-4448df73-3c02-469b-9dc2-9531ecc26801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422457608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2422457608 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/39.kmac_entropy_refresh.3365261010 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 9342427772 ps |
| CPU time | 182.09 seconds |
| Started | May 26 02:59:44 PM PDT 24 |
| Finished | May 26 03:02:47 PM PDT 24 |
| Peak memory | 239620 kb |
| Host | smart-ac867dd8-ce37-4c0d-b63a-50389a9eb66c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365261010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3365261010 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/39.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/39.kmac_error.3558028072 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3041667832 ps |
| CPU time | 101.37 seconds |
| Started | May 26 02:59:45 PM PDT 24 |
| Finished | May 26 03:01:27 PM PDT 24 |
| Peak memory | 240148 kb |
| Host | smart-92e27853-0d17-43b6-98eb-121b1749ec8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3558028072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3558028072 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_error/latest |
| Test location | /workspace/coverage/default/39.kmac_key_error.280329438 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1327826613 ps |
| CPU time | 7.08 seconds |
| Started | May 26 02:59:44 PM PDT 24 |
| Finished | May 26 02:59:51 PM PDT 24 |
| Peak memory | 215284 kb |
| Host | smart-72883cc0-9445-45a1-bb43-21b62e18dffa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280329438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.280329438 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_key_error/latest |
| Test location | /workspace/coverage/default/39.kmac_lc_escalation.3412958551 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 299708950 ps |
| CPU time | 6.57 seconds |
| Started | May 26 02:59:51 PM PDT 24 |
| Finished | May 26 02:59:58 PM PDT 24 |
| Peak memory | 223844 kb |
| Host | smart-ab5fbd1e-958e-4cd8-a387-b66963818b31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412958551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3412958551 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/39.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/39.kmac_long_msg_and_output.2582915745 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 26547679060 ps |
| CPU time | 2276.86 seconds |
| Started | May 26 02:59:29 PM PDT 24 |
| Finished | May 26 03:37:27 PM PDT 24 |
| Peak memory | 450624 kb |
| Host | smart-98155b53-612b-4ce4-89a7-0e5f88cac5cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582915745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a nd_output.2582915745 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/39.kmac_sideload.4094083474 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4417999847 ps |
| CPU time | 346.86 seconds |
| Started | May 26 02:59:37 PM PDT 24 |
| Finished | May 26 03:05:25 PM PDT 24 |
| Peak memory | 251336 kb |
| Host | smart-fc56da33-2c1d-4edc-90b8-286827d62ff9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094083474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.4094083474 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_sideload/latest |
| Test location | /workspace/coverage/default/39.kmac_smoke.1552922301 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 817301765 ps |
| CPU time | 21.04 seconds |
| Started | May 26 02:59:30 PM PDT 24 |
| Finished | May 26 02:59:51 PM PDT 24 |
| Peak memory | 218796 kb |
| Host | smart-da08825f-8766-4998-b73c-61ec547edbe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552922301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1552922301 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_smoke/latest |
| Test location | /workspace/coverage/default/39.kmac_stress_all.1942573851 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 18958424328 ps |
| CPU time | 248.6 seconds |
| Started | May 26 02:59:52 PM PDT 24 |
| Finished | May 26 03:04:01 PM PDT 24 |
| Peak memory | 242128 kb |
| Host | smart-0a84ba77-79f6-4ef0-9ef2-d551edc930a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1942573851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1942573851 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/39.kmac_test_vectors_kmac.262443123 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 177644391 ps |
| CPU time | 5.09 seconds |
| Started | May 26 02:59:44 PM PDT 24 |
| Finished | May 26 02:59:50 PM PDT 24 |
| Peak memory | 215512 kb |
| Host | smart-f7611fda-7221-4452-af88-442f46bb4eb7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262443123 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 39.kmac_test_vectors_kmac.262443123 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3777760575 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 66167887 ps |
| CPU time | 4.24 seconds |
| Started | May 26 02:59:44 PM PDT 24 |
| Finished | May 26 02:59:49 PM PDT 24 |
| Peak memory | 215536 kb |
| Host | smart-caf0f665-ebe2-449d-a304-fc696fc499ef |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777760575 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3777760575 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/39.kmac_test_vectors_sha3_224.831576349 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 188808312317 ps |
| CPU time | 1973.06 seconds |
| Started | May 26 02:59:37 PM PDT 24 |
| Finished | May 26 03:32:31 PM PDT 24 |
| Peak memory | 374024 kb |
| Host | smart-9023e634-4d47-4519-bec5-0342f254e410 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=831576349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.831576349 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/39.kmac_test_vectors_sha3_256.689707384 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 256085896578 ps |
| CPU time | 1734.49 seconds |
| Started | May 26 02:59:38 PM PDT 24 |
| Finished | May 26 03:28:34 PM PDT 24 |
| Peak memory | 376252 kb |
| Host | smart-590f08b9-f840-48b7-a90f-03ff8b7bd0c5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=689707384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.689707384 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/39.kmac_test_vectors_sha3_384.1494645525 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 286771269158 ps |
| CPU time | 1399.92 seconds |
| Started | May 26 02:59:39 PM PDT 24 |
| Finished | May 26 03:23:00 PM PDT 24 |
| Peak memory | 329412 kb |
| Host | smart-5d600047-1af5-4a12-a242-975156ed3162 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1494645525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.1494645525 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/39.kmac_test_vectors_sha3_512.3605884275 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 40163017309 ps |
| CPU time | 893.12 seconds |
| Started | May 26 02:59:38 PM PDT 24 |
| Finished | May 26 03:14:32 PM PDT 24 |
| Peak memory | 297824 kb |
| Host | smart-e5f5238f-04c3-4952-973a-dd9718a6b743 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3605884275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.3605884275 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/39.kmac_test_vectors_shake_128.854864022 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 51339668485 ps |
| CPU time | 4349.97 seconds |
| Started | May 26 02:59:37 PM PDT 24 |
| Finished | May 26 04:12:09 PM PDT 24 |
| Peak memory | 650268 kb |
| Host | smart-22acc39a-a58b-4c91-a3c4-096b39761cf3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=854864022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.854864022 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/39.kmac_test_vectors_shake_256.3379938429 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 43657917003 ps |
| CPU time | 3669.37 seconds |
| Started | May 26 02:59:38 PM PDT 24 |
| Finished | May 26 04:00:49 PM PDT 24 |
| Peak memory | 568748 kb |
| Host | smart-9d141ee4-b2a5-4aaa-bee6-2db11d4d1a77 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3379938429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.3379938429 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/39.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/4.kmac_alert_test.4247989559 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 69099955 ps |
| CPU time | 0.77 seconds |
| Started | May 26 02:55:11 PM PDT 24 |
| Finished | May 26 02:55:14 PM PDT 24 |
| Peak memory | 204872 kb |
| Host | smart-d5067106-67cf-40d5-ab8b-1c30bd96260e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247989559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.4247989559 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/4.kmac_app.1330443124 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 732013724 ps |
| CPU time | 20.64 seconds |
| Started | May 26 02:55:06 PM PDT 24 |
| Finished | May 26 02:55:29 PM PDT 24 |
| Peak memory | 223664 kb |
| Host | smart-82d79a74-4063-4f8b-9605-d23d7e90722a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330443124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1330443124 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_app/latest |
| Test location | /workspace/coverage/default/4.kmac_app_with_partial_data.3266946287 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 10832695036 ps |
| CPU time | 95.33 seconds |
| Started | May 26 02:55:08 PM PDT 24 |
| Finished | May 26 02:56:46 PM PDT 24 |
| Peak memory | 230444 kb |
| Host | smart-eea94699-6093-49bb-8394-3cda173a1fae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266946287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3266946287 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/4.kmac_burst_write.1543746609 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 32485735111 ps |
| CPU time | 766.35 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 03:08:07 PM PDT 24 |
| Peak memory | 231516 kb |
| Host | smart-8e5908b4-9f6d-492e-844a-57a56c636f39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543746609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1543746609 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/4.kmac_edn_timeout_error.1845205850 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1472411995 ps |
| CPU time | 37.43 seconds |
| Started | May 26 02:55:06 PM PDT 24 |
| Finished | May 26 02:55:46 PM PDT 24 |
| Peak memory | 225196 kb |
| Host | smart-a48a086f-87c1-410c-a183-5bde99c414da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1845205850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1845205850 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/4.kmac_entropy_mode_error.4117893737 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2360761084 ps |
| CPU time | 27.18 seconds |
| Started | May 26 02:55:03 PM PDT 24 |
| Finished | May 26 02:55:33 PM PDT 24 |
| Peak memory | 223444 kb |
| Host | smart-d9e751a8-185c-4414-b0fc-58a521ebb925 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4117893737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.4117893737 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/4.kmac_entropy_ready_error.1948876016 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1275216110 ps |
| CPU time | 14.31 seconds |
| Started | May 26 02:55:11 PM PDT 24 |
| Finished | May 26 02:55:28 PM PDT 24 |
| Peak memory | 215480 kb |
| Host | smart-585cc1fb-fbff-42c7-9987-0c3045bcc179 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948876016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1948876016 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/4.kmac_entropy_refresh.3748215469 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 13756057161 ps |
| CPU time | 238.14 seconds |
| Started | May 26 02:55:07 PM PDT 24 |
| Finished | May 26 02:59:08 PM PDT 24 |
| Peak memory | 240340 kb |
| Host | smart-9f0d09ad-fca5-47b0-bfbb-921607b57b8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748215469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3748215469 +enable_masking=0 +s w_key_masked=0 |
| Directory | /workspace/4.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/4.kmac_error.2857824247 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13973066312 ps |
| CPU time | 215.24 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 02:58:50 PM PDT 24 |
| Peak memory | 254920 kb |
| Host | smart-fa963a54-1f7c-477a-a71c-76f21a153925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857824247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2857824247 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_error/latest |
| Test location | /workspace/coverage/default/4.kmac_key_error.1820447377 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 7813352480 ps |
| CPU time | 9.65 seconds |
| Started | May 26 02:55:08 PM PDT 24 |
| Finished | May 26 02:55:20 PM PDT 24 |
| Peak memory | 215588 kb |
| Host | smart-2601324b-8928-49a5-9b69-e03a0dc378ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820447377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1820447377 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_key_error/latest |
| Test location | /workspace/coverage/default/4.kmac_lc_escalation.863535609 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 50350650 ps |
| CPU time | 1.31 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:55:19 PM PDT 24 |
| Peak memory | 219044 kb |
| Host | smart-2ce070e3-fec6-4b0e-b7ff-19ab5b6c15de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863535609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.863535609 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/4.kmac_long_msg_and_output.2119772929 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 96741104266 ps |
| CPU time | 2152.3 seconds |
| Started | May 26 02:55:00 PM PDT 24 |
| Finished | May 26 03:30:56 PM PDT 24 |
| Peak memory | 407372 kb |
| Host | smart-de483711-bf02-4839-bec3-677b0ecf77c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119772929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.2119772929 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/4.kmac_mubi.1114883699 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 1602239046 ps |
| CPU time | 22.08 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 02:55:29 PM PDT 24 |
| Peak memory | 220540 kb |
| Host | smart-3789b665-b2e5-4ca3-a74b-46766ad187a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114883699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1114883699 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_mubi/latest |
| Test location | /workspace/coverage/default/4.kmac_sideload.2040399968 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 23641109197 ps |
| CPU time | 126.24 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 02:57:22 PM PDT 24 |
| Peak memory | 228988 kb |
| Host | smart-862d3bf6-1769-4af9-9747-a2dd2a11c19c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040399968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2040399968 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_sideload/latest |
| Test location | /workspace/coverage/default/4.kmac_smoke.3610343608 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4239402621 ps |
| CPU time | 25.63 seconds |
| Started | May 26 02:55:04 PM PDT 24 |
| Finished | May 26 02:55:32 PM PDT 24 |
| Peak memory | 219660 kb |
| Host | smart-81aaddfa-15da-41bc-a666-63c21db58e46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610343608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3610343608 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_smoke/latest |
| Test location | /workspace/coverage/default/4.kmac_stress_all.956720997 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4362149843 ps |
| CPU time | 179.77 seconds |
| Started | May 26 02:55:11 PM PDT 24 |
| Finished | May 26 02:58:13 PM PDT 24 |
| Peak memory | 224764 kb |
| Host | smart-b6bab391-3c17-4ffd-a08a-4ff4a3be5e08 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=956720997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.956720997 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/4.kmac_test_vectors_kmac.2829738859 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 238454311 ps |
| CPU time | 4.62 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 02:55:25 PM PDT 24 |
| Peak memory | 215536 kb |
| Host | smart-2f1a6122-187d-4010-a243-aadf16b03200 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829738859 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.kmac_test_vectors_kmac.2829738859 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3530260731 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 103286025 ps |
| CPU time | 4.34 seconds |
| Started | May 26 02:55:06 PM PDT 24 |
| Finished | May 26 02:55:13 PM PDT 24 |
| Peak memory | 208868 kb |
| Host | smart-0144b82d-04be-41dd-911a-cb96df42c2c4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530260731 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3530260731 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/4.kmac_test_vectors_sha3_224.2729403322 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 373477241736 ps |
| CPU time | 1582.08 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 03:21:41 PM PDT 24 |
| Peak memory | 388956 kb |
| Host | smart-779f9c06-c9f5-4564-a28e-25ff2a5c10c9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2729403322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2729403322 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/4.kmac_test_vectors_sha3_256.4204312902 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 74016489909 ps |
| CPU time | 1462.37 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 03:19:38 PM PDT 24 |
| Peak memory | 374720 kb |
| Host | smart-5e237693-797e-4dfe-92e1-85a41c41d9e2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4204312902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.4204312902 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2420239098 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 13686423634 ps |
| CPU time | 1137.83 seconds |
| Started | May 26 02:55:06 PM PDT 24 |
| Finished | May 26 03:14:07 PM PDT 24 |
| Peak memory | 329616 kb |
| Host | smart-b641d103-ebf9-4aa6-80f9-adb85a65436c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2420239098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2420239098 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/4.kmac_test_vectors_sha3_512.2748064484 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 9879241013 ps |
| CPU time | 753.08 seconds |
| Started | May 26 02:55:09 PM PDT 24 |
| Finished | May 26 03:07:44 PM PDT 24 |
| Peak memory | 293500 kb |
| Host | smart-48d1b317-a57e-442c-abf8-a105de09dff1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2748064484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2748064484 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/4.kmac_test_vectors_shake_128.953216762 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 533096587793 ps |
| CPU time | 5466.89 seconds |
| Started | May 26 02:55:06 PM PDT 24 |
| Finished | May 26 04:26:16 PM PDT 24 |
| Peak memory | 646068 kb |
| Host | smart-2b10ab4a-7233-423a-8c46-03fb167adc1b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=953216762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.953216762 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/4.kmac_test_vectors_shake_256.2628633626 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 641384666821 ps |
| CPU time | 4271.89 seconds |
| Started | May 26 02:55:11 PM PDT 24 |
| Finished | May 26 04:06:26 PM PDT 24 |
| Peak memory | 550888 kb |
| Host | smart-a42caf3f-49f3-407b-a176-c4fd02fbe387 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2628633626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2628633626 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/40.kmac_alert_test.18532537 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 16189037 ps |
| CPU time | 0.82 seconds |
| Started | May 26 03:00:00 PM PDT 24 |
| Finished | May 26 03:00:01 PM PDT 24 |
| Peak memory | 204856 kb |
| Host | smart-ff9afd74-9858-4a14-8362-6ab09506c71a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18532537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.18532537 +enable_mas king=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/40.kmac_app.802655550 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 9827146625 ps |
| CPU time | 251.7 seconds |
| Started | May 26 02:59:58 PM PDT 24 |
| Finished | May 26 03:04:11 PM PDT 24 |
| Peak memory | 240832 kb |
| Host | smart-7e477d64-3c59-4715-95fe-018dd4cf3c46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802655550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.802655550 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_app/latest |
| Test location | /workspace/coverage/default/40.kmac_burst_write.252069235 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 87209361 ps |
| CPU time | 7.38 seconds |
| Started | May 26 02:59:52 PM PDT 24 |
| Finished | May 26 03:00:00 PM PDT 24 |
| Peak memory | 217736 kb |
| Host | smart-6822fbd9-1322-4522-a033-d7f2d1c2bc2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252069235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.252069235 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/40.kmac_entropy_refresh.3557547015 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 36178086297 ps |
| CPU time | 165.56 seconds |
| Started | May 26 02:59:59 PM PDT 24 |
| Finished | May 26 03:02:45 PM PDT 24 |
| Peak memory | 234516 kb |
| Host | smart-b8ceb9fc-7b6b-494e-9cb8-48c998d02801 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557547015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3557547015 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/40.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/40.kmac_error.3945109151 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2460537107 ps |
| CPU time | 68.26 seconds |
| Started | May 26 02:59:58 PM PDT 24 |
| Finished | May 26 03:01:07 PM PDT 24 |
| Peak memory | 240116 kb |
| Host | smart-73a10160-1484-448e-9fc6-ebe4b90c1604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945109151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3945109151 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_error/latest |
| Test location | /workspace/coverage/default/40.kmac_key_error.3558426815 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 357545277 ps |
| CPU time | 2.23 seconds |
| Started | May 26 02:59:58 PM PDT 24 |
| Finished | May 26 03:00:01 PM PDT 24 |
| Peak memory | 207088 kb |
| Host | smart-3f3d2f2f-70dd-43ba-8964-2eb2aeaea5e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3558426815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3558426815 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_key_error/latest |
| Test location | /workspace/coverage/default/40.kmac_lc_escalation.2711462974 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 37922942 ps |
| CPU time | 1.2 seconds |
| Started | May 26 02:59:59 PM PDT 24 |
| Finished | May 26 03:00:01 PM PDT 24 |
| Peak memory | 215312 kb |
| Host | smart-c8c82b01-81ca-46e6-8dc9-d7e04257ee40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711462974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2711462974 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/40.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/40.kmac_long_msg_and_output.712957500 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 46990862153 ps |
| CPU time | 1241.62 seconds |
| Started | May 26 02:59:50 PM PDT 24 |
| Finished | May 26 03:20:33 PM PDT 24 |
| Peak memory | 333620 kb |
| Host | smart-34f03ebf-af48-416b-9f26-c4b7d4f23b07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712957500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an d_output.712957500 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/40.kmac_sideload.1124264460 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 348763437 ps |
| CPU time | 25.24 seconds |
| Started | May 26 02:59:53 PM PDT 24 |
| Finished | May 26 03:00:19 PM PDT 24 |
| Peak memory | 219836 kb |
| Host | smart-1e9ebd51-2945-4c8f-8348-6339a03e526f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124264460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1124264460 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_sideload/latest |
| Test location | /workspace/coverage/default/40.kmac_smoke.4021446462 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 3540630088 ps |
| CPU time | 16.99 seconds |
| Started | May 26 02:59:52 PM PDT 24 |
| Finished | May 26 03:00:10 PM PDT 24 |
| Peak memory | 221620 kb |
| Host | smart-5a03aae5-e681-471b-abca-9a83b412bcbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021446462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.4021446462 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_smoke/latest |
| Test location | /workspace/coverage/default/40.kmac_stress_all.144125142 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 122767059377 ps |
| CPU time | 470.82 seconds |
| Started | May 26 03:00:00 PM PDT 24 |
| Finished | May 26 03:07:51 PM PDT 24 |
| Peak memory | 289672 kb |
| Host | smart-1eab1a77-70ff-4897-9769-2a305a18fa0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=144125142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.144125142 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/40.kmac_test_vectors_kmac.2713102852 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 914694305 ps |
| CPU time | 4.64 seconds |
| Started | May 26 02:59:53 PM PDT 24 |
| Finished | May 26 02:59:58 PM PDT 24 |
| Peak memory | 215532 kb |
| Host | smart-a6325be4-d4af-478b-9f15-c7589315b98c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713102852 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.kmac_test_vectors_kmac.2713102852 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1838442068 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 245739890 ps |
| CPU time | 5.23 seconds |
| Started | May 26 02:59:52 PM PDT 24 |
| Finished | May 26 02:59:58 PM PDT 24 |
| Peak memory | 215580 kb |
| Host | smart-2be31b02-7e7e-47da-9cad-ebf9b846dbba |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838442068 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1838442068 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/40.kmac_test_vectors_sha3_224.320586508 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 67304027212 ps |
| CPU time | 1870.91 seconds |
| Started | May 26 02:59:50 PM PDT 24 |
| Finished | May 26 03:31:02 PM PDT 24 |
| Peak memory | 379032 kb |
| Host | smart-ac7f76f8-3ff2-437c-ab71-d19fd35d9ec9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=320586508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.320586508 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/40.kmac_test_vectors_sha3_256.3013237055 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 72853427976 ps |
| CPU time | 1521.11 seconds |
| Started | May 26 02:59:52 PM PDT 24 |
| Finished | May 26 03:25:14 PM PDT 24 |
| Peak memory | 368236 kb |
| Host | smart-cd30a528-595c-4954-b61e-ed9d0f4d828e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3013237055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.3013237055 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/40.kmac_test_vectors_sha3_384.1967121868 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 101801786805 ps |
| CPU time | 1317.1 seconds |
| Started | May 26 02:59:51 PM PDT 24 |
| Finished | May 26 03:21:49 PM PDT 24 |
| Peak memory | 334060 kb |
| Host | smart-4c5214bd-875c-4a99-842d-3139b2a87d49 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1967121868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.1967121868 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/40.kmac_test_vectors_sha3_512.2720345507 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 858289706849 ps |
| CPU time | 992.87 seconds |
| Started | May 26 02:59:51 PM PDT 24 |
| Finished | May 26 03:16:24 PM PDT 24 |
| Peak memory | 297636 kb |
| Host | smart-6cc2ef4d-8713-4b8f-8cf9-3c4f35b54f8b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2720345507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.2720345507 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/40.kmac_test_vectors_shake_128.1980523234 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 714914210790 ps |
| CPU time | 4977.72 seconds |
| Started | May 26 02:59:51 PM PDT 24 |
| Finished | May 26 04:22:50 PM PDT 24 |
| Peak memory | 647920 kb |
| Host | smart-af8e5e09-60c7-40a8-af2a-ab65089e69b9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1980523234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.1980523234 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/40.kmac_test_vectors_shake_256.3052065821 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 146067528676 ps |
| CPU time | 4454.69 seconds |
| Started | May 26 02:59:53 PM PDT 24 |
| Finished | May 26 04:14:09 PM PDT 24 |
| Peak memory | 565368 kb |
| Host | smart-d6d892ad-11c7-400c-8062-4d2ab96428c6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3052065821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3052065821 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/40.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/41.kmac_alert_test.1901579627 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 27799926 ps |
| CPU time | 0.77 seconds |
| Started | May 26 03:00:19 PM PDT 24 |
| Finished | May 26 03:00:21 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-0efca487-9f5a-4fcb-be2d-bd53b2e42203 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901579627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1901579627 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/41.kmac_app.2846002892 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 23221675655 ps |
| CPU time | 240.81 seconds |
| Started | May 26 03:00:10 PM PDT 24 |
| Finished | May 26 03:04:11 PM PDT 24 |
| Peak memory | 245240 kb |
| Host | smart-0a6bf2ee-6eeb-463b-84ce-2ed092f0383e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846002892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2846002892 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_app/latest |
| Test location | /workspace/coverage/default/41.kmac_burst_write.2244087413 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 41032387624 ps |
| CPU time | 477.64 seconds |
| Started | May 26 03:00:01 PM PDT 24 |
| Finished | May 26 03:07:59 PM PDT 24 |
| Peak memory | 228628 kb |
| Host | smart-d4a580f4-dd3e-4ce1-ae9b-3e7838c61509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244087413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.2244087413 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/41.kmac_entropy_refresh.2262064520 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 384725164 ps |
| CPU time | 13.94 seconds |
| Started | May 26 03:00:10 PM PDT 24 |
| Finished | May 26 03:00:24 PM PDT 24 |
| Peak memory | 223648 kb |
| Host | smart-5449eb77-4d05-4077-b587-241d552bc159 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262064520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2262064520 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/41.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/41.kmac_error.394510905 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 165341572852 ps |
| CPU time | 288.88 seconds |
| Started | May 26 03:00:10 PM PDT 24 |
| Finished | May 26 03:05:00 PM PDT 24 |
| Peak memory | 249456 kb |
| Host | smart-caa47d71-bfad-452b-9b9b-df239a5f95f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394510905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.394510905 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_error/latest |
| Test location | /workspace/coverage/default/41.kmac_key_error.1380032170 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 6868152737 ps |
| CPU time | 8.07 seconds |
| Started | May 26 03:00:17 PM PDT 24 |
| Finished | May 26 03:00:26 PM PDT 24 |
| Peak memory | 215336 kb |
| Host | smart-2b048d17-ccb4-4f00-9b8b-344c9265a0ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380032170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1380032170 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_key_error/latest |
| Test location | /workspace/coverage/default/41.kmac_lc_escalation.1259539957 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 122247936 ps |
| CPU time | 1.16 seconds |
| Started | May 26 03:00:19 PM PDT 24 |
| Finished | May 26 03:00:21 PM PDT 24 |
| Peak memory | 215268 kb |
| Host | smart-5a5187c4-515a-491a-a53c-7e10023e4478 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259539957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1259539957 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/41.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/41.kmac_long_msg_and_output.4179051246 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 12298606183 ps |
| CPU time | 1062.45 seconds |
| Started | May 26 02:59:57 PM PDT 24 |
| Finished | May 26 03:17:41 PM PDT 24 |
| Peak memory | 333292 kb |
| Host | smart-7bc7b034-1311-4879-9033-e67f348feb05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179051246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a nd_output.4179051246 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/41.kmac_sideload.3347299951 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1453420042 ps |
| CPU time | 113.82 seconds |
| Started | May 26 02:59:58 PM PDT 24 |
| Finished | May 26 03:01:52 PM PDT 24 |
| Peak memory | 229896 kb |
| Host | smart-d5102832-d394-4289-ae7b-ca9cc7e35a5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347299951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3347299951 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_sideload/latest |
| Test location | /workspace/coverage/default/41.kmac_smoke.3163739912 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 295399502 ps |
| CPU time | 14.33 seconds |
| Started | May 26 02:59:59 PM PDT 24 |
| Finished | May 26 03:00:14 PM PDT 24 |
| Peak memory | 218572 kb |
| Host | smart-6ad79f92-ef97-45b0-a1f9-ea907d43fdf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163739912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3163739912 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_smoke/latest |
| Test location | /workspace/coverage/default/41.kmac_stress_all.191909598 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 25952049844 ps |
| CPU time | 201.56 seconds |
| Started | May 26 03:00:19 PM PDT 24 |
| Finished | May 26 03:03:42 PM PDT 24 |
| Peak memory | 248368 kb |
| Host | smart-6229e301-8477-498c-8a96-0bee550dc9aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=191909598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.191909598 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/41.kmac_test_vectors_kmac.1198023448 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 110596377 ps |
| CPU time | 3.96 seconds |
| Started | May 26 03:00:10 PM PDT 24 |
| Finished | May 26 03:00:15 PM PDT 24 |
| Peak memory | 215600 kb |
| Host | smart-f2dc6d88-4ab4-4ed7-9fec-2d9de1bc0e95 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198023448 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.kmac_test_vectors_kmac.1198023448 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.4207024654 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1024868264 ps |
| CPU time | 4.64 seconds |
| Started | May 26 03:00:10 PM PDT 24 |
| Finished | May 26 03:00:15 PM PDT 24 |
| Peak memory | 215564 kb |
| Host | smart-f2cf80c8-19f7-46bf-bb15-b4f60aaf12e1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207024654 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.4207024654 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/41.kmac_test_vectors_sha3_224.757647229 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 359022047633 ps |
| CPU time | 1763.28 seconds |
| Started | May 26 02:59:58 PM PDT 24 |
| Finished | May 26 03:29:22 PM PDT 24 |
| Peak memory | 390316 kb |
| Host | smart-a6b725ce-8e2d-4c50-8da3-18539c187fc0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=757647229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.757647229 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/41.kmac_test_vectors_sha3_256.1245762741 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 18825773113 ps |
| CPU time | 1502.13 seconds |
| Started | May 26 02:59:58 PM PDT 24 |
| Finished | May 26 03:25:01 PM PDT 24 |
| Peak memory | 376724 kb |
| Host | smart-827aba3a-b7af-4009-a799-09fa9dad6cc5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1245762741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1245762741 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/41.kmac_test_vectors_sha3_384.167867334 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 47057173220 ps |
| CPU time | 1388.49 seconds |
| Started | May 26 03:00:09 PM PDT 24 |
| Finished | May 26 03:23:18 PM PDT 24 |
| Peak memory | 335292 kb |
| Host | smart-4e62a642-ff00-437f-acd0-98320446acef |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=167867334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.167867334 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/41.kmac_test_vectors_sha3_512.1989286540 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 39755627126 ps |
| CPU time | 803.63 seconds |
| Started | May 26 03:00:09 PM PDT 24 |
| Finished | May 26 03:13:33 PM PDT 24 |
| Peak memory | 295868 kb |
| Host | smart-7c620749-52b4-48bc-9344-2d5da91fff97 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1989286540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1989286540 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/41.kmac_test_vectors_shake_128.401362271 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 1013790575198 ps |
| CPU time | 5432.29 seconds |
| Started | May 26 03:00:10 PM PDT 24 |
| Finished | May 26 04:30:44 PM PDT 24 |
| Peak memory | 637988 kb |
| Host | smart-b7981881-3010-42fc-afec-b99ca19ec152 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=401362271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.401362271 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/41.kmac_test_vectors_shake_256.2101939054 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 182533791457 ps |
| CPU time | 3612.44 seconds |
| Started | May 26 03:00:10 PM PDT 24 |
| Finished | May 26 04:00:23 PM PDT 24 |
| Peak memory | 571820 kb |
| Host | smart-7bcc3de8-0b52-4e45-88c1-8e307e19fc81 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2101939054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2101939054 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/41.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/42.kmac_alert_test.2824849701 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 179244864 ps |
| CPU time | 0.88 seconds |
| Started | May 26 03:00:25 PM PDT 24 |
| Finished | May 26 03:00:27 PM PDT 24 |
| Peak memory | 204848 kb |
| Host | smart-fc9981c0-be25-46bc-8fb3-4b7e6ac220dd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824849701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2824849701 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/42.kmac_app.2507804548 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 5269737377 ps |
| CPU time | 133.84 seconds |
| Started | May 26 03:00:25 PM PDT 24 |
| Finished | May 26 03:02:39 PM PDT 24 |
| Peak memory | 234624 kb |
| Host | smart-e3e1a260-8d21-4b52-be61-1704b0306eb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507804548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2507804548 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_app/latest |
| Test location | /workspace/coverage/default/42.kmac_burst_write.3440233433 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 81920368655 ps |
| CPU time | 505.71 seconds |
| Started | May 26 03:00:18 PM PDT 24 |
| Finished | May 26 03:08:45 PM PDT 24 |
| Peak memory | 230212 kb |
| Host | smart-c6b90eca-82c7-4027-a4b5-817166ac0ec8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440233433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3440233433 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/42.kmac_entropy_refresh.2581760390 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1802488440 ps |
| CPU time | 13.83 seconds |
| Started | May 26 03:00:23 PM PDT 24 |
| Finished | May 26 03:00:38 PM PDT 24 |
| Peak memory | 217656 kb |
| Host | smart-4c69aa6a-6cae-4979-961b-286be760075e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581760390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2581760390 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/42.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/42.kmac_error.2375459552 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4533985270 ps |
| CPU time | 85.71 seconds |
| Started | May 26 03:00:24 PM PDT 24 |
| Finished | May 26 03:01:50 PM PDT 24 |
| Peak memory | 237180 kb |
| Host | smart-35e57944-5b63-4288-8960-08334bdcdef9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2375459552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2375459552 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_error/latest |
| Test location | /workspace/coverage/default/42.kmac_key_error.2783559794 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 3808530402 ps |
| CPU time | 6.08 seconds |
| Started | May 26 03:00:27 PM PDT 24 |
| Finished | May 26 03:00:33 PM PDT 24 |
| Peak memory | 207132 kb |
| Host | smart-28ae7b66-6bfe-4ec1-b00d-375b5ebace49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783559794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2783559794 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_key_error/latest |
| Test location | /workspace/coverage/default/42.kmac_lc_escalation.585969460 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 45165410 ps |
| CPU time | 1.13 seconds |
| Started | May 26 03:00:25 PM PDT 24 |
| Finished | May 26 03:00:27 PM PDT 24 |
| Peak memory | 215268 kb |
| Host | smart-d727d32d-42b4-4ecb-8bed-d3542db87807 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585969460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.585969460 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/42.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/42.kmac_long_msg_and_output.1567848293 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 103939730447 ps |
| CPU time | 2208.83 seconds |
| Started | May 26 03:00:18 PM PDT 24 |
| Finished | May 26 03:37:08 PM PDT 24 |
| Peak memory | 412232 kb |
| Host | smart-87fb8505-579d-4f1f-aed3-abd142f614b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567848293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a nd_output.1567848293 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/42.kmac_sideload.2258364689 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 38730898399 ps |
| CPU time | 377.04 seconds |
| Started | May 26 03:00:18 PM PDT 24 |
| Finished | May 26 03:06:36 PM PDT 24 |
| Peak memory | 247296 kb |
| Host | smart-c20fe133-7c03-4e50-bf4a-c86c37a4b656 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258364689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2258364689 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_sideload/latest |
| Test location | /workspace/coverage/default/42.kmac_smoke.2884287292 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 27712937800 ps |
| CPU time | 48.58 seconds |
| Started | May 26 03:00:17 PM PDT 24 |
| Finished | May 26 03:01:06 PM PDT 24 |
| Peak memory | 221296 kb |
| Host | smart-514b0428-c0bf-4d4b-a3ba-d8cc87b16b77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2884287292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2884287292 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_smoke/latest |
| Test location | /workspace/coverage/default/42.kmac_stress_all.2848761054 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 61468787823 ps |
| CPU time | 1128.16 seconds |
| Started | May 26 03:00:28 PM PDT 24 |
| Finished | May 26 03:19:17 PM PDT 24 |
| Peak memory | 387140 kb |
| Host | smart-1060061e-2d6d-4fa8-a884-1ac5363e13c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2848761054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2848761054 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/42.kmac_test_vectors_kmac.2222590800 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 716344480 ps |
| CPU time | 4.68 seconds |
| Started | May 26 03:00:17 PM PDT 24 |
| Finished | May 26 03:00:23 PM PDT 24 |
| Peak memory | 215576 kb |
| Host | smart-0c3d0095-8954-44dd-9e60-9284188d5926 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222590800 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.kmac_test_vectors_kmac.2222590800 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2480109619 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 245497166 ps |
| CPU time | 3.96 seconds |
| Started | May 26 03:00:17 PM PDT 24 |
| Finished | May 26 03:00:22 PM PDT 24 |
| Peak memory | 215660 kb |
| Host | smart-8c427990-b99a-4aa2-a729-5a8c54c21585 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480109619 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2480109619 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/42.kmac_test_vectors_sha3_224.2407198571 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 445570523283 ps |
| CPU time | 2148.41 seconds |
| Started | May 26 03:00:16 PM PDT 24 |
| Finished | May 26 03:36:05 PM PDT 24 |
| Peak memory | 394744 kb |
| Host | smart-e9886377-caaa-4162-b16a-7dfc650f3b34 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2407198571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2407198571 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/42.kmac_test_vectors_sha3_256.2002785491 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 81357519955 ps |
| CPU time | 1489.55 seconds |
| Started | May 26 03:00:18 PM PDT 24 |
| Finished | May 26 03:25:09 PM PDT 24 |
| Peak memory | 376788 kb |
| Host | smart-1ad2b960-9a81-4e1d-a0d8-bead13f61df5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2002785491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.2002785491 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/42.kmac_test_vectors_sha3_384.2245107369 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 177020994690 ps |
| CPU time | 1328.05 seconds |
| Started | May 26 03:00:19 PM PDT 24 |
| Finished | May 26 03:22:28 PM PDT 24 |
| Peak memory | 330884 kb |
| Host | smart-c1fef805-7848-41a3-82f5-289191bb37ce |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2245107369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2245107369 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/42.kmac_test_vectors_sha3_512.3357339429 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 19472239535 ps |
| CPU time | 818.01 seconds |
| Started | May 26 03:00:18 PM PDT 24 |
| Finished | May 26 03:13:57 PM PDT 24 |
| Peak memory | 295804 kb |
| Host | smart-a6d2e874-9f2b-449b-9f5a-0ef0059cec04 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3357339429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3357339429 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/42.kmac_test_vectors_shake_128.3030523062 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 249933661684 ps |
| CPU time | 4931.08 seconds |
| Started | May 26 03:00:18 PM PDT 24 |
| Finished | May 26 04:22:31 PM PDT 24 |
| Peak memory | 626108 kb |
| Host | smart-55efcb39-9a96-49c5-b70f-b264502415e6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3030523062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3030523062 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/42.kmac_test_vectors_shake_256.3929985943 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 42693188954 ps |
| CPU time | 3509.12 seconds |
| Started | May 26 03:00:17 PM PDT 24 |
| Finished | May 26 03:58:47 PM PDT 24 |
| Peak memory | 540192 kb |
| Host | smart-8f5a1a0e-dc1a-49d4-975e-3b9eee8b8b87 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3929985943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.3929985943 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/42.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/43.kmac_alert_test.322378757 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 63363961 ps |
| CPU time | 0.87 seconds |
| Started | May 26 03:00:40 PM PDT 24 |
| Finished | May 26 03:00:42 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-620d5285-dbd9-4c44-95c0-5bb9fef1851e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322378757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.322378757 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/43.kmac_app.3254704644 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 30896355590 ps |
| CPU time | 195.04 seconds |
| Started | May 26 03:00:31 PM PDT 24 |
| Finished | May 26 03:03:46 PM PDT 24 |
| Peak memory | 236128 kb |
| Host | smart-5d97cbcf-4dd8-4065-80c1-b03a107ec213 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254704644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3254704644 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_app/latest |
| Test location | /workspace/coverage/default/43.kmac_burst_write.1520535702 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 57317235702 ps |
| CPU time | 387.57 seconds |
| Started | May 26 03:00:33 PM PDT 24 |
| Finished | May 26 03:07:01 PM PDT 24 |
| Peak memory | 226832 kb |
| Host | smart-5a83807b-f1dc-410d-9c01-30dc1c9b5843 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1520535702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1520535702 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/43.kmac_entropy_refresh.1627736477 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 54127997513 ps |
| CPU time | 253.05 seconds |
| Started | May 26 03:00:32 PM PDT 24 |
| Finished | May 26 03:04:46 PM PDT 24 |
| Peak memory | 243568 kb |
| Host | smart-bea15240-7cc6-4070-9b40-108c0ab07ca4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627736477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1627736477 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/43.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/43.kmac_error.2186224366 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 20557394859 ps |
| CPU time | 100.07 seconds |
| Started | May 26 03:00:41 PM PDT 24 |
| Finished | May 26 03:02:22 PM PDT 24 |
| Peak memory | 240148 kb |
| Host | smart-1933076f-35d6-4144-9a86-4e175910d559 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186224366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2186224366 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_error/latest |
| Test location | /workspace/coverage/default/43.kmac_key_error.1240972547 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 956407621 ps |
| CPU time | 2.92 seconds |
| Started | May 26 03:00:39 PM PDT 24 |
| Finished | May 26 03:00:43 PM PDT 24 |
| Peak memory | 207100 kb |
| Host | smart-c9060a2b-8fd6-4e1c-beaa-5cf08681ce55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240972547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1240972547 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_key_error/latest |
| Test location | /workspace/coverage/default/43.kmac_lc_escalation.206928153 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 34537549 ps |
| CPU time | 1.22 seconds |
| Started | May 26 03:00:39 PM PDT 24 |
| Finished | May 26 03:00:41 PM PDT 24 |
| Peak memory | 215316 kb |
| Host | smart-6e08c57f-7542-4e33-ae8b-c2c984cafec9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206928153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.206928153 +enable_masking=0 +sw_key _masked=0 |
| Directory | /workspace/43.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/43.kmac_long_msg_and_output.900747475 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 37379855164 ps |
| CPU time | 823.48 seconds |
| Started | May 26 03:00:25 PM PDT 24 |
| Finished | May 26 03:14:10 PM PDT 24 |
| Peak memory | 291836 kb |
| Host | smart-8db83391-732f-4519-8353-b7451fa0bf4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900747475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_an d_output.900747475 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/43.kmac_sideload.4139262983 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 25973285431 ps |
| CPU time | 202.74 seconds |
| Started | May 26 03:00:33 PM PDT 24 |
| Finished | May 26 03:03:57 PM PDT 24 |
| Peak memory | 238644 kb |
| Host | smart-19041b48-69a9-499d-a906-43c02522609d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139262983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.4139262983 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_sideload/latest |
| Test location | /workspace/coverage/default/43.kmac_smoke.552415149 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3329087189 ps |
| CPU time | 37.94 seconds |
| Started | May 26 03:00:25 PM PDT 24 |
| Finished | May 26 03:01:03 PM PDT 24 |
| Peak memory | 223680 kb |
| Host | smart-ace8a420-78f5-4d63-9b4d-e22125a9f9fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552415149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.552415149 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_smoke/latest |
| Test location | /workspace/coverage/default/43.kmac_stress_all.3947994074 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 27765104086 ps |
| CPU time | 632.05 seconds |
| Started | May 26 03:00:40 PM PDT 24 |
| Finished | May 26 03:11:13 PM PDT 24 |
| Peak memory | 320580 kb |
| Host | smart-2021ecdf-6e73-43c9-a8fc-b553a1d91f6b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3947994074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3947994074 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/43.kmac_stress_all_with_rand_reset.3575644321 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 33448443180 ps |
| CPU time | 1424.78 seconds |
| Started | May 26 03:00:39 PM PDT 24 |
| Finished | May 26 03:24:26 PM PDT 24 |
| Peak memory | 359468 kb |
| Host | smart-53a3c2b5-439d-44cb-a3ce-cfe87fdf5c1f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3575644321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all_with_rand_reset.3575644321 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.kmac_test_vectors_kmac.4020006696 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 1227328321 ps |
| CPU time | 4.74 seconds |
| Started | May 26 03:00:34 PM PDT 24 |
| Finished | May 26 03:00:40 PM PDT 24 |
| Peak memory | 215592 kb |
| Host | smart-8ad854a2-d8d8-4174-940b-c9e1d9045daf |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020006696 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.kmac_test_vectors_kmac.4020006696 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.330082343 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 230096698 ps |
| CPU time | 4.52 seconds |
| Started | May 26 03:00:35 PM PDT 24 |
| Finished | May 26 03:00:40 PM PDT 24 |
| Peak memory | 215556 kb |
| Host | smart-29c7e6e8-174d-4627-adde-e42a37476e80 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330082343 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 43.kmac_test_vectors_kmac_xof.330082343 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/43.kmac_test_vectors_sha3_224.3983534840 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 788417085621 ps |
| CPU time | 2059.07 seconds |
| Started | May 26 03:00:35 PM PDT 24 |
| Finished | May 26 03:34:55 PM PDT 24 |
| Peak memory | 374600 kb |
| Host | smart-b22f467e-e030-4e67-97b1-c2f8bd67b0f2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3983534840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3983534840 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/43.kmac_test_vectors_sha3_256.3036299210 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 188434426006 ps |
| CPU time | 1860.87 seconds |
| Started | May 26 03:00:34 PM PDT 24 |
| Finished | May 26 03:31:36 PM PDT 24 |
| Peak memory | 377356 kb |
| Host | smart-714a4141-2ead-47af-8ba4-799233d17cf5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3036299210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3036299210 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/43.kmac_test_vectors_sha3_384.2351672319 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 139740842461 ps |
| CPU time | 1429.79 seconds |
| Started | May 26 03:00:32 PM PDT 24 |
| Finished | May 26 03:24:22 PM PDT 24 |
| Peak memory | 328192 kb |
| Host | smart-668a2c85-fb37-4972-9332-99b6c8d8767d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2351672319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2351672319 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/43.kmac_test_vectors_sha3_512.3248103325 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 245858751922 ps |
| CPU time | 1014.53 seconds |
| Started | May 26 03:00:34 PM PDT 24 |
| Finished | May 26 03:17:29 PM PDT 24 |
| Peak memory | 296376 kb |
| Host | smart-fd0e8da7-3fae-4c41-b1fb-84fb026eb8ad |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3248103325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.3248103325 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/43.kmac_test_vectors_shake_128.2186109277 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 556877023940 ps |
| CPU time | 5398.94 seconds |
| Started | May 26 03:00:32 PM PDT 24 |
| Finished | May 26 04:30:32 PM PDT 24 |
| Peak memory | 646912 kb |
| Host | smart-fc0fd6b6-e4f7-43ab-b98e-a8ef85fe5604 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2186109277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.2186109277 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/43.kmac_test_vectors_shake_256.2398618315 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 190408744918 ps |
| CPU time | 4196 seconds |
| Started | May 26 03:00:32 PM PDT 24 |
| Finished | May 26 04:10:29 PM PDT 24 |
| Peak memory | 553464 kb |
| Host | smart-b3d952b8-ea9b-491f-a956-a22da4cffcc4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2398618315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2398618315 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/43.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/44.kmac_alert_test.1266632375 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 53087208 ps |
| CPU time | 0.79 seconds |
| Started | May 26 03:00:55 PM PDT 24 |
| Finished | May 26 03:00:57 PM PDT 24 |
| Peak memory | 204852 kb |
| Host | smart-d66cb383-7a7d-4def-be53-aa1b3394321c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266632375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1266632375 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/44.kmac_app.1988802882 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 23699641292 ps |
| CPU time | 140.73 seconds |
| Started | May 26 03:00:55 PM PDT 24 |
| Finished | May 26 03:03:16 PM PDT 24 |
| Peak memory | 232160 kb |
| Host | smart-ec6e815a-5eac-4363-bd23-67975a91765c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988802882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1988802882 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_app/latest |
| Test location | /workspace/coverage/default/44.kmac_burst_write.3269173016 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 19589514745 ps |
| CPU time | 443.89 seconds |
| Started | May 26 03:00:40 PM PDT 24 |
| Finished | May 26 03:08:05 PM PDT 24 |
| Peak memory | 228480 kb |
| Host | smart-7ade3034-11d5-4dea-8ea7-f92aea3150a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269173016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.3269173016 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/44.kmac_entropy_refresh.545362863 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 44918458979 ps |
| CPU time | 248.86 seconds |
| Started | May 26 03:00:55 PM PDT 24 |
| Finished | May 26 03:05:05 PM PDT 24 |
| Peak memory | 239852 kb |
| Host | smart-fbb882bc-703a-48b5-9d05-895a2c71af99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545362863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.545362863 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspace/44.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/44.kmac_error.504516597 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 16576354253 ps |
| CPU time | 312.89 seconds |
| Started | May 26 03:00:55 PM PDT 24 |
| Finished | May 26 03:06:09 PM PDT 24 |
| Peak memory | 249212 kb |
| Host | smart-0174dc0d-7ccb-4f95-82d9-27048c94c164 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504516597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.504516597 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_error/latest |
| Test location | /workspace/coverage/default/44.kmac_key_error.2296664262 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1632947740 ps |
| CPU time | 7.8 seconds |
| Started | May 26 03:00:55 PM PDT 24 |
| Finished | May 26 03:01:03 PM PDT 24 |
| Peak memory | 207116 kb |
| Host | smart-097a6db3-6373-4545-bf28-01c250e73827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2296664262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2296664262 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_key_error/latest |
| Test location | /workspace/coverage/default/44.kmac_lc_escalation.2433145379 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 61976851 ps |
| CPU time | 1.42 seconds |
| Started | May 26 03:00:56 PM PDT 24 |
| Finished | May 26 03:00:58 PM PDT 24 |
| Peak memory | 215336 kb |
| Host | smart-266ee941-0937-4900-aeea-ded0d1cb189f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433145379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2433145379 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/44.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/44.kmac_long_msg_and_output.220735122 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 9009807743 ps |
| CPU time | 749.2 seconds |
| Started | May 26 03:00:40 PM PDT 24 |
| Finished | May 26 03:13:10 PM PDT 24 |
| Peak memory | 300880 kb |
| Host | smart-d7bbab86-5526-4c7c-a394-4e071f0d44ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220735122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an d_output.220735122 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/44.kmac_sideload.134782105 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 199414037487 ps |
| CPU time | 440.98 seconds |
| Started | May 26 03:00:38 PM PDT 24 |
| Finished | May 26 03:08:00 PM PDT 24 |
| Peak memory | 247100 kb |
| Host | smart-0163777f-c5bc-4968-ac58-7626bc6b96b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134782105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.134782105 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_sideload/latest |
| Test location | /workspace/coverage/default/44.kmac_smoke.2473078106 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 6829658983 ps |
| CPU time | 53.59 seconds |
| Started | May 26 03:00:40 PM PDT 24 |
| Finished | May 26 03:01:35 PM PDT 24 |
| Peak memory | 219192 kb |
| Host | smart-5b4512c5-3269-433d-9c4a-cdec1e933810 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473078106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2473078106 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_smoke/latest |
| Test location | /workspace/coverage/default/44.kmac_stress_all.4169872689 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 73631445529 ps |
| CPU time | 503.16 seconds |
| Started | May 26 03:00:55 PM PDT 24 |
| Finished | May 26 03:09:20 PM PDT 24 |
| Peak memory | 306088 kb |
| Host | smart-cf063e6b-94fc-4bb0-92f5-021a0c2273f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4169872689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4169872689 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/44.kmac_test_vectors_kmac.1131577002 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 247710194 ps |
| CPU time | 5.04 seconds |
| Started | May 26 03:00:53 PM PDT 24 |
| Finished | May 26 03:00:59 PM PDT 24 |
| Peak memory | 215492 kb |
| Host | smart-09ad6095-ed43-4ebb-a429-b077ad423611 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131577002 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.kmac_test_vectors_kmac.1131577002 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.394896209 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 174600442 ps |
| CPU time | 4.56 seconds |
| Started | May 26 03:00:55 PM PDT 24 |
| Finished | May 26 03:01:01 PM PDT 24 |
| Peak memory | 215664 kb |
| Host | smart-03fa1e3e-27b9-4588-87c8-f22ac5b297ea |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394896209 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 44.kmac_test_vectors_kmac_xof.394896209 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/44.kmac_test_vectors_sha3_224.3155635895 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 68430007601 ps |
| CPU time | 1878.25 seconds |
| Started | May 26 03:00:45 PM PDT 24 |
| Finished | May 26 03:32:04 PM PDT 24 |
| Peak memory | 400080 kb |
| Host | smart-46ced9de-dd33-473a-be59-be89d0948970 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3155635895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.3155635895 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/44.kmac_test_vectors_sha3_256.3792152438 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 60513705829 ps |
| CPU time | 1629.26 seconds |
| Started | May 26 03:00:47 PM PDT 24 |
| Finished | May 26 03:27:57 PM PDT 24 |
| Peak memory | 370228 kb |
| Host | smart-e47bf45a-1596-413f-b630-3c59892fca1d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3792152438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.3792152438 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/44.kmac_test_vectors_sha3_384.4269231592 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 14081816025 ps |
| CPU time | 1173.88 seconds |
| Started | May 26 03:00:45 PM PDT 24 |
| Finished | May 26 03:20:20 PM PDT 24 |
| Peak memory | 332116 kb |
| Host | smart-bb6fea40-f0db-4995-972c-2da4909d5e68 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4269231592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.4269231592 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/44.kmac_test_vectors_sha3_512.759323600 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 102649672617 ps |
| CPU time | 1136.39 seconds |
| Started | May 26 03:00:46 PM PDT 24 |
| Finished | May 26 03:19:43 PM PDT 24 |
| Peak memory | 296524 kb |
| Host | smart-f13cb6dd-7149-45ad-859f-5132dff90c84 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=759323600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.759323600 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/44.kmac_test_vectors_shake_128.3250915040 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 170500861860 ps |
| CPU time | 5117.76 seconds |
| Started | May 26 03:00:47 PM PDT 24 |
| Finished | May 26 04:26:06 PM PDT 24 |
| Peak memory | 641200 kb |
| Host | smart-e3d374c9-a475-4dcd-bd30-62e98208cc05 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3250915040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.3250915040 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/44.kmac_test_vectors_shake_256.1625574684 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 44177713936 ps |
| CPU time | 3330.98 seconds |
| Started | May 26 03:00:46 PM PDT 24 |
| Finished | May 26 03:56:18 PM PDT 24 |
| Peak memory | 552940 kb |
| Host | smart-2c895747-5e53-472d-8b70-3e7c36a08021 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1625574684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.1625574684 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/44.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/45.kmac_alert_test.1595115870 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 14074062 ps |
| CPU time | 0.83 seconds |
| Started | May 26 03:01:11 PM PDT 24 |
| Finished | May 26 03:01:12 PM PDT 24 |
| Peak memory | 204848 kb |
| Host | smart-82589edc-c74e-47f4-8c52-a8b5a6a98026 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595115870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1595115870 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/45.kmac_app.2977813759 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 3110834196 ps |
| CPU time | 158.68 seconds |
| Started | May 26 03:01:03 PM PDT 24 |
| Finished | May 26 03:03:43 PM PDT 24 |
| Peak memory | 237476 kb |
| Host | smart-48efc6e8-1e24-44c1-aafc-1a8555f90ef1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977813759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2977813759 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_app/latest |
| Test location | /workspace/coverage/default/45.kmac_burst_write.1705795822 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5350108294 ps |
| CPU time | 111.72 seconds |
| Started | May 26 03:01:05 PM PDT 24 |
| Finished | May 26 03:02:58 PM PDT 24 |
| Peak memory | 221400 kb |
| Host | smart-43580d47-1aaa-4123-97f2-4fff2e227aa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705795822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1705795822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/45.kmac_entropy_refresh.3671795192 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3539318163 ps |
| CPU time | 77.19 seconds |
| Started | May 26 03:01:04 PM PDT 24 |
| Finished | May 26 03:02:22 PM PDT 24 |
| Peak memory | 226076 kb |
| Host | smart-c7d82d07-a147-43b1-a89c-e94f8f5a96f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671795192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3671795192 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/45.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/45.kmac_error.3013119482 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4015502606 ps |
| CPU time | 288.84 seconds |
| Started | May 26 03:01:04 PM PDT 24 |
| Finished | May 26 03:05:54 PM PDT 24 |
| Peak memory | 248560 kb |
| Host | smart-afc3ac5c-d5e8-422f-8c61-84788634514b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013119482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3013119482 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_error/latest |
| Test location | /workspace/coverage/default/45.kmac_key_error.3981388062 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4553909053 ps |
| CPU time | 6.68 seconds |
| Started | May 26 03:01:09 PM PDT 24 |
| Finished | May 26 03:01:17 PM PDT 24 |
| Peak memory | 215516 kb |
| Host | smart-9c946aae-fbbd-4531-a003-441ea47fd27d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981388062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3981388062 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_key_error/latest |
| Test location | /workspace/coverage/default/45.kmac_long_msg_and_output.1897566269 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 456573199566 ps |
| CPU time | 2360.56 seconds |
| Started | May 26 03:01:09 PM PDT 24 |
| Finished | May 26 03:40:30 PM PDT 24 |
| Peak memory | 436792 kb |
| Host | smart-f14e69d5-f210-4b5a-af92-d2ccfc589cf4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897566269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.1897566269 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/45.kmac_sideload.648406319 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 17496248530 ps |
| CPU time | 366.73 seconds |
| Started | May 26 03:01:10 PM PDT 24 |
| Finished | May 26 03:07:18 PM PDT 24 |
| Peak memory | 244692 kb |
| Host | smart-09bd61e0-ed07-45f8-b207-751aa7bf206f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648406319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.648406319 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_sideload/latest |
| Test location | /workspace/coverage/default/45.kmac_smoke.210367876 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 467744000 ps |
| CPU time | 8.88 seconds |
| Started | May 26 03:00:55 PM PDT 24 |
| Finished | May 26 03:01:05 PM PDT 24 |
| Peak memory | 218804 kb |
| Host | smart-8f6465f1-9bd4-4d01-a0ce-ffbaf271c122 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210367876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.210367876 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_smoke/latest |
| Test location | /workspace/coverage/default/45.kmac_stress_all.902957139 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 41929057065 ps |
| CPU time | 500.35 seconds |
| Started | May 26 03:01:10 PM PDT 24 |
| Finished | May 26 03:09:31 PM PDT 24 |
| Peak memory | 314232 kb |
| Host | smart-88682f88-74b3-4b57-a90e-dbac73deb4de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=902957139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.902957139 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/45.kmac_test_vectors_kmac.1102928686 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 259741180 ps |
| CPU time | 4.03 seconds |
| Started | May 26 03:01:04 PM PDT 24 |
| Finished | May 26 03:01:09 PM PDT 24 |
| Peak memory | 215540 kb |
| Host | smart-f01efefd-2b4e-45fe-9882-70ec56b8a191 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102928686 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.kmac_test_vectors_kmac.1102928686 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.260399476 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 169523623 ps |
| CPU time | 4.29 seconds |
| Started | May 26 03:01:04 PM PDT 24 |
| Finished | May 26 03:01:09 PM PDT 24 |
| Peak memory | 215584 kb |
| Host | smart-6b6e7ab5-fb3a-4082-9277-813d3e004713 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260399476 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 45.kmac_test_vectors_kmac_xof.260399476 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/45.kmac_test_vectors_sha3_224.829696546 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 19348257289 ps |
| CPU time | 1714.48 seconds |
| Started | May 26 03:01:04 PM PDT 24 |
| Finished | May 26 03:29:39 PM PDT 24 |
| Peak memory | 394188 kb |
| Host | smart-3a0fc659-9339-408c-9b02-fa928ca4401e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=829696546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.829696546 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/45.kmac_test_vectors_sha3_256.1735674846 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 380655624537 ps |
| CPU time | 1995.77 seconds |
| Started | May 26 03:01:11 PM PDT 24 |
| Finished | May 26 03:34:28 PM PDT 24 |
| Peak memory | 373440 kb |
| Host | smart-281d0701-721e-40d3-a784-ef01ba024f5e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1735674846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.1735674846 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/45.kmac_test_vectors_sha3_384.3106691971 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 249629194049 ps |
| CPU time | 1346.07 seconds |
| Started | May 26 03:01:04 PM PDT 24 |
| Finished | May 26 03:23:31 PM PDT 24 |
| Peak memory | 336412 kb |
| Host | smart-4d970ed5-a37e-48ca-a76b-3232d46664d2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3106691971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.3106691971 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/45.kmac_test_vectors_sha3_512.2667971650 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 37969564052 ps |
| CPU time | 805.97 seconds |
| Started | May 26 03:01:04 PM PDT 24 |
| Finished | May 26 03:14:31 PM PDT 24 |
| Peak memory | 294748 kb |
| Host | smart-b97ea749-5e8e-42a3-8f0f-496963935dda |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2667971650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.2667971650 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/45.kmac_test_vectors_shake_128.1045170486 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 52391330689 ps |
| CPU time | 4082.86 seconds |
| Started | May 26 03:01:11 PM PDT 24 |
| Finished | May 26 04:09:16 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-5fc8d700-e4ab-483d-9168-cf856acf7cd0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1045170486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1045170486 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/45.kmac_test_vectors_shake_256.760608332 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 307638879964 ps |
| CPU time | 3136.99 seconds |
| Started | May 26 03:01:11 PM PDT 24 |
| Finished | May 26 03:53:30 PM PDT 24 |
| Peak memory | 556412 kb |
| Host | smart-696770ce-1125-4bfa-8395-e9f1b55eb371 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=760608332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.760608332 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/45.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/46.kmac_alert_test.1720730706 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 57166464 ps |
| CPU time | 0.85 seconds |
| Started | May 26 03:01:38 PM PDT 24 |
| Finished | May 26 03:01:40 PM PDT 24 |
| Peak memory | 204848 kb |
| Host | smart-e5b71357-34b6-477b-87ef-a5122c2f195e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720730706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1720730706 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/46.kmac_app.1646614423 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2542937403 ps |
| CPU time | 51.48 seconds |
| Started | May 26 03:01:25 PM PDT 24 |
| Finished | May 26 03:02:17 PM PDT 24 |
| Peak memory | 222972 kb |
| Host | smart-a5985382-ffa2-45f3-8dfb-49601700ebd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646614423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1646614423 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_app/latest |
| Test location | /workspace/coverage/default/46.kmac_burst_write.1341065805 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 26902906919 ps |
| CPU time | 426.34 seconds |
| Started | May 26 03:01:18 PM PDT 24 |
| Finished | May 26 03:08:25 PM PDT 24 |
| Peak memory | 229776 kb |
| Host | smart-383e9f10-0dc8-45c7-bff8-270ee176dc5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341065805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1341065805 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/46.kmac_entropy_refresh.489478370 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 15257225062 ps |
| CPU time | 151.57 seconds |
| Started | May 26 03:01:25 PM PDT 24 |
| Finished | May 26 03:03:57 PM PDT 24 |
| Peak memory | 234600 kb |
| Host | smart-e7c0b503-c04e-453b-9792-bd5a65b39acc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489478370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.489478370 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspace/46.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/46.kmac_error.1805672299 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9519942622 ps |
| CPU time | 254.11 seconds |
| Started | May 26 03:01:32 PM PDT 24 |
| Finished | May 26 03:05:47 PM PDT 24 |
| Peak memory | 253552 kb |
| Host | smart-453f766b-bb92-467b-8770-e2e25a3d4261 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805672299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1805672299 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_error/latest |
| Test location | /workspace/coverage/default/46.kmac_key_error.1642420820 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4288340836 ps |
| CPU time | 7.41 seconds |
| Started | May 26 03:01:32 PM PDT 24 |
| Finished | May 26 03:01:40 PM PDT 24 |
| Peak memory | 215328 kb |
| Host | smart-10e42c2f-061c-43e9-bdbf-20d2ea98adec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642420820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1642420820 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_key_error/latest |
| Test location | /workspace/coverage/default/46.kmac_lc_escalation.3788869844 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 58366863 ps |
| CPU time | 1.11 seconds |
| Started | May 26 03:01:32 PM PDT 24 |
| Finished | May 26 03:01:34 PM PDT 24 |
| Peak memory | 215304 kb |
| Host | smart-8042e5b8-3ac2-4ac2-bd4a-0b025dba9a4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788869844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3788869844 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/46.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/46.kmac_long_msg_and_output.62443738 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 142079832047 ps |
| CPU time | 915.05 seconds |
| Started | May 26 03:01:15 PM PDT 24 |
| Finished | May 26 03:16:31 PM PDT 24 |
| Peak memory | 304452 kb |
| Host | smart-4aa87194-d1a9-49f8-9196-31425815c022 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62443738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and _output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and _output.62443738 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/46.kmac_sideload.3540277454 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 9975290077 ps |
| CPU time | 189.51 seconds |
| Started | May 26 03:01:17 PM PDT 24 |
| Finished | May 26 03:04:27 PM PDT 24 |
| Peak memory | 240092 kb |
| Host | smart-ca64774d-191a-45c6-bcc0-06e768b22186 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540277454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3540277454 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_sideload/latest |
| Test location | /workspace/coverage/default/46.kmac_smoke.2516595866 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4170306325 ps |
| CPU time | 67.73 seconds |
| Started | May 26 03:01:17 PM PDT 24 |
| Finished | May 26 03:02:26 PM PDT 24 |
| Peak memory | 219248 kb |
| Host | smart-b5c723ea-b0ce-471a-8ce7-f4ba43efc455 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516595866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2516595866 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_smoke/latest |
| Test location | /workspace/coverage/default/46.kmac_stress_all.597598295 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 20933695474 ps |
| CPU time | 1486.08 seconds |
| Started | May 26 03:01:33 PM PDT 24 |
| Finished | May 26 03:26:20 PM PDT 24 |
| Peak memory | 425960 kb |
| Host | smart-1bc877e9-f65f-4a88-9434-a35d80075227 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=597598295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.597598295 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/46.kmac_test_vectors_kmac.3979627475 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 136208531 ps |
| CPU time | 4.12 seconds |
| Started | May 26 03:01:24 PM PDT 24 |
| Finished | May 26 03:01:29 PM PDT 24 |
| Peak memory | 215528 kb |
| Host | smart-dc1f2d04-7e08-4ba5-91c1-0c2bd6dc110c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979627475 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.kmac_test_vectors_kmac.3979627475 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1268772649 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2660996763 ps |
| CPU time | 4.48 seconds |
| Started | May 26 03:01:24 PM PDT 24 |
| Finished | May 26 03:01:29 PM PDT 24 |
| Peak memory | 215588 kb |
| Host | smart-8e1362e2-8a7e-4bd4-8b8c-492da6a33821 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268772649 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1268772649 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/46.kmac_test_vectors_sha3_224.1495999528 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 37682823727 ps |
| CPU time | 1527.12 seconds |
| Started | May 26 03:01:17 PM PDT 24 |
| Finished | May 26 03:26:45 PM PDT 24 |
| Peak memory | 392252 kb |
| Host | smart-781e08d3-85ad-47e1-97a0-3ac3f87831dd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1495999528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.1495999528 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/46.kmac_test_vectors_sha3_256.2433987036 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 178062829924 ps |
| CPU time | 1462.27 seconds |
| Started | May 26 03:01:17 PM PDT 24 |
| Finished | May 26 03:25:40 PM PDT 24 |
| Peak memory | 375088 kb |
| Host | smart-eb89afb7-acfb-4029-957f-313034d9128f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2433987036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.2433987036 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/46.kmac_test_vectors_sha3_384.2608828203 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 318339646605 ps |
| CPU time | 1389.8 seconds |
| Started | May 26 03:01:17 PM PDT 24 |
| Finished | May 26 03:24:27 PM PDT 24 |
| Peak memory | 334056 kb |
| Host | smart-6b598706-bf76-40c9-b191-534feff48b81 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2608828203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2608828203 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/46.kmac_test_vectors_sha3_512.3397973342 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 123729942881 ps |
| CPU time | 976.47 seconds |
| Started | May 26 03:01:27 PM PDT 24 |
| Finished | May 26 03:17:45 PM PDT 24 |
| Peak memory | 298612 kb |
| Host | smart-b9d04582-4edc-4b9c-94b2-e0f3d2741b55 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3397973342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.3397973342 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/46.kmac_test_vectors_shake_128.3893155329 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 747863646799 ps |
| CPU time | 4991 seconds |
| Started | May 26 03:01:24 PM PDT 24 |
| Finished | May 26 04:24:36 PM PDT 24 |
| Peak memory | 650304 kb |
| Host | smart-ddf4936a-ed81-42ef-868a-1e533053a5de |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3893155329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.3893155329 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/46.kmac_test_vectors_shake_256.1833243382 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 545868259541 ps |
| CPU time | 3581.59 seconds |
| Started | May 26 03:01:24 PM PDT 24 |
| Finished | May 26 04:01:07 PM PDT 24 |
| Peak memory | 568820 kb |
| Host | smart-c1139f8b-6b80-4d8f-bc86-8949c171137a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1833243382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1833243382 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/46.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/47.kmac_alert_test.1946540333 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 21371132 ps |
| CPU time | 0.75 seconds |
| Started | May 26 03:01:55 PM PDT 24 |
| Finished | May 26 03:01:56 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-7c1c0727-c175-4228-8835-cd75af740ae7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946540333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1946540333 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/47.kmac_app.641982189 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 24176628866 ps |
| CPU time | 306.7 seconds |
| Started | May 26 03:01:48 PM PDT 24 |
| Finished | May 26 03:06:55 PM PDT 24 |
| Peak memory | 246220 kb |
| Host | smart-d1d82b6b-805b-40cc-afe0-53af7d613c3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641982189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.641982189 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_app/latest |
| Test location | /workspace/coverage/default/47.kmac_burst_write.2066798298 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 19820351639 ps |
| CPU time | 205.01 seconds |
| Started | May 26 03:01:39 PM PDT 24 |
| Finished | May 26 03:05:04 PM PDT 24 |
| Peak memory | 226464 kb |
| Host | smart-3643f9b2-3541-4f43-b42a-aed3fe084c03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2066798298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2066798298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/47.kmac_entropy_refresh.2559097608 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 79278117311 ps |
| CPU time | 282.44 seconds |
| Started | May 26 03:01:46 PM PDT 24 |
| Finished | May 26 03:06:29 PM PDT 24 |
| Peak memory | 238860 kb |
| Host | smart-53fc093b-4c9b-4666-9962-98e45801a633 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559097608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2559097608 +enable_masking=0 + sw_key_masked=0 |
| Directory | /workspace/47.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/47.kmac_error.3585389895 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5658746805 ps |
| CPU time | 120.7 seconds |
| Started | May 26 03:01:48 PM PDT 24 |
| Finished | May 26 03:03:49 PM PDT 24 |
| Peak memory | 240172 kb |
| Host | smart-70d4a99d-0bec-4bb9-9f9a-d93fe0010281 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585389895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3585389895 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_error/latest |
| Test location | /workspace/coverage/default/47.kmac_lc_escalation.3068253483 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 125215250 ps |
| CPU time | 1.31 seconds |
| Started | May 26 03:01:46 PM PDT 24 |
| Finished | May 26 03:01:47 PM PDT 24 |
| Peak memory | 215432 kb |
| Host | smart-c5b39813-8625-42c3-b5e8-f715e79d8767 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068253483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3068253483 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/47.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/47.kmac_long_msg_and_output.2410758529 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 108446410545 ps |
| CPU time | 1533.35 seconds |
| Started | May 26 03:01:41 PM PDT 24 |
| Finished | May 26 03:27:15 PM PDT 24 |
| Peak memory | 398384 kb |
| Host | smart-8004f750-c86d-4c83-9582-8add40aa7dfc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410758529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a nd_output.2410758529 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/47.kmac_sideload.4124140122 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 81439079467 ps |
| CPU time | 409.18 seconds |
| Started | May 26 03:01:39 PM PDT 24 |
| Finished | May 26 03:08:29 PM PDT 24 |
| Peak memory | 247912 kb |
| Host | smart-94af687f-af98-4f81-85da-bb3f4245c8c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124140122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.4124140122 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_sideload/latest |
| Test location | /workspace/coverage/default/47.kmac_smoke.4216648232 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 1087326592 ps |
| CPU time | 7.5 seconds |
| Started | May 26 03:01:39 PM PDT 24 |
| Finished | May 26 03:01:48 PM PDT 24 |
| Peak memory | 215960 kb |
| Host | smart-3614827f-f464-46ac-a488-a4db674146c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216648232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.4216648232 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_smoke/latest |
| Test location | /workspace/coverage/default/47.kmac_stress_all.3389101085 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 93421520717 ps |
| CPU time | 1561.62 seconds |
| Started | May 26 03:01:54 PM PDT 24 |
| Finished | May 26 03:27:57 PM PDT 24 |
| Peak memory | 412512 kb |
| Host | smart-6ca64dd9-4664-4cf2-8b02-a779ef995187 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3389101085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3389101085 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/47.kmac_test_vectors_kmac.3725345298 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 70875455 ps |
| CPU time | 4.56 seconds |
| Started | May 26 03:01:45 PM PDT 24 |
| Finished | May 26 03:01:50 PM PDT 24 |
| Peak memory | 215596 kb |
| Host | smart-4f7c084b-1d51-4d26-a40f-72fb88777e46 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725345298 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.3725345298 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3115552611 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 178091355 ps |
| CPU time | 4.3 seconds |
| Started | May 26 03:01:46 PM PDT 24 |
| Finished | May 26 03:01:51 PM PDT 24 |
| Peak memory | 208760 kb |
| Host | smart-a60b035f-3cd8-4a83-81d6-e47d35c1bb5d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115552611 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3115552611 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/47.kmac_test_vectors_sha3_224.2862493302 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 38552262749 ps |
| CPU time | 1527.63 seconds |
| Started | May 26 03:01:39 PM PDT 24 |
| Finished | May 26 03:27:07 PM PDT 24 |
| Peak memory | 378196 kb |
| Host | smart-ff2753dc-265a-4b60-acf8-03103495f265 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2862493302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.2862493302 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/47.kmac_test_vectors_sha3_256.2002439459 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 62567196551 ps |
| CPU time | 1704.53 seconds |
| Started | May 26 03:01:38 PM PDT 24 |
| Finished | May 26 03:30:03 PM PDT 24 |
| Peak memory | 368196 kb |
| Host | smart-c542fc49-3865-4687-8be7-5be145180d92 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2002439459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2002439459 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1286059042 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 72401764401 ps |
| CPU time | 1401.85 seconds |
| Started | May 26 03:01:40 PM PDT 24 |
| Finished | May 26 03:25:03 PM PDT 24 |
| Peak memory | 332244 kb |
| Host | smart-b722c5d1-437d-4aa9-ad75-880813d37e72 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1286059042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1286059042 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/47.kmac_test_vectors_sha3_512.838623205 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 33047902394 ps |
| CPU time | 845.23 seconds |
| Started | May 26 03:01:47 PM PDT 24 |
| Finished | May 26 03:15:53 PM PDT 24 |
| Peak memory | 293276 kb |
| Host | smart-08fedc8c-367e-4f0b-a885-60ef7bf473b2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=838623205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.838623205 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/47.kmac_test_vectors_shake_128.2582614032 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 197875131375 ps |
| CPU time | 4403.56 seconds |
| Started | May 26 03:01:45 PM PDT 24 |
| Finished | May 26 04:15:10 PM PDT 24 |
| Peak memory | 662240 kb |
| Host | smart-3d59743d-4ceb-4566-af1e-5bb78752421b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2582614032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.2582614032 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/47.kmac_test_vectors_shake_256.4137391623 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 43800548992 ps |
| CPU time | 3577.3 seconds |
| Started | May 26 03:01:46 PM PDT 24 |
| Finished | May 26 04:01:24 PM PDT 24 |
| Peak memory | 565672 kb |
| Host | smart-e252ed89-c5f0-4567-97b7-ba0e10b89fb9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4137391623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.4137391623 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/47.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/48.kmac_alert_test.428479143 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 69752479 ps |
| CPU time | 0.75 seconds |
| Started | May 26 03:02:22 PM PDT 24 |
| Finished | May 26 03:02:24 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-b5de65d7-7b7b-4d8c-bf92-acd52c697908 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428479143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.428479143 +enable_m asking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/48.kmac_app.1098675408 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 3159698517 ps |
| CPU time | 170.19 seconds |
| Started | May 26 03:02:22 PM PDT 24 |
| Finished | May 26 03:05:13 PM PDT 24 |
| Peak memory | 236048 kb |
| Host | smart-963c4ac8-4e5b-4a68-b729-551755f78037 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098675408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1098675408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_app/latest |
| Test location | /workspace/coverage/default/48.kmac_burst_write.2590418923 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 20554264492 ps |
| CPU time | 483.19 seconds |
| Started | May 26 03:02:03 PM PDT 24 |
| Finished | May 26 03:10:07 PM PDT 24 |
| Peak memory | 229768 kb |
| Host | smart-51c0f449-50d5-4835-b30a-8c415cf2cf3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590418923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2590418923 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/48.kmac_entropy_refresh.38918785 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 9831190310 ps |
| CPU time | 178.99 seconds |
| Started | May 26 03:02:23 PM PDT 24 |
| Finished | May 26 03:05:22 PM PDT 24 |
| Peak memory | 240312 kb |
| Host | smart-5b4acc31-f23d-42d5-8b90-07c6245dc400 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38918785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.38918785 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/48.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/48.kmac_error.4233721084 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 102726195342 ps |
| CPU time | 402.66 seconds |
| Started | May 26 03:02:22 PM PDT 24 |
| Finished | May 26 03:09:06 PM PDT 24 |
| Peak memory | 264660 kb |
| Host | smart-c3b73ab2-29d4-4c2a-968d-2705a520cb9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233721084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.4233721084 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_error/latest |
| Test location | /workspace/coverage/default/48.kmac_key_error.2624094017 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3293158141 ps |
| CPU time | 5.13 seconds |
| Started | May 26 03:02:25 PM PDT 24 |
| Finished | May 26 03:02:31 PM PDT 24 |
| Peak memory | 207172 kb |
| Host | smart-0ef8f905-9358-49e5-afca-2cad523299fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624094017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2624094017 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_key_error/latest |
| Test location | /workspace/coverage/default/48.kmac_lc_escalation.3031435388 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 34564302 ps |
| CPU time | 1.21 seconds |
| Started | May 26 03:02:22 PM PDT 24 |
| Finished | May 26 03:02:24 PM PDT 24 |
| Peak memory | 215376 kb |
| Host | smart-e3763f67-4ad4-4308-9a74-00959e2c1f5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031435388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3031435388 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/48.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/48.kmac_long_msg_and_output.374693636 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 9481834673 ps |
| CPU time | 206.72 seconds |
| Started | May 26 03:01:55 PM PDT 24 |
| Finished | May 26 03:05:23 PM PDT 24 |
| Peak memory | 240120 kb |
| Host | smart-ad9f9c55-bda3-4adf-a9d7-660d95f82a14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374693636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_an d_output.374693636 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/48.kmac_sideload.2834020273 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 12920961766 ps |
| CPU time | 347.84 seconds |
| Started | May 26 03:01:53 PM PDT 24 |
| Finished | May 26 03:07:42 PM PDT 24 |
| Peak memory | 246732 kb |
| Host | smart-ea0d2684-b493-4003-bbd9-78f7dd1bf42d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834020273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2834020273 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_sideload/latest |
| Test location | /workspace/coverage/default/48.kmac_smoke.2519648563 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1024854895 ps |
| CPU time | 51.12 seconds |
| Started | May 26 03:01:55 PM PDT 24 |
| Finished | May 26 03:02:47 PM PDT 24 |
| Peak memory | 217628 kb |
| Host | smart-0f46703c-eadb-41a6-9b33-140663d5b094 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519648563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2519648563 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_smoke/latest |
| Test location | /workspace/coverage/default/48.kmac_stress_all.3996261733 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 90995868659 ps |
| CPU time | 460.34 seconds |
| Started | May 26 03:02:24 PM PDT 24 |
| Finished | May 26 03:10:05 PM PDT 24 |
| Peak memory | 284140 kb |
| Host | smart-60714523-5a50-4527-b89a-7e05398993c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3996261733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3996261733 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/48.kmac_stress_all_with_rand_reset.668181693 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 669292371258 ps |
| CPU time | 1692.69 seconds |
| Started | May 26 03:02:23 PM PDT 24 |
| Finished | May 26 03:30:36 PM PDT 24 |
| Peak memory | 314856 kb |
| Host | smart-c62fa854-01ad-4075-af54-a620f8aa82bd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=668181693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all_with_rand_reset.668181693 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.kmac_test_vectors_kmac.2899148089 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 126361664 ps |
| CPU time | 4.09 seconds |
| Started | May 26 03:02:23 PM PDT 24 |
| Finished | May 26 03:02:28 PM PDT 24 |
| Peak memory | 215484 kb |
| Host | smart-84578c07-3731-44b7-b7ea-2b4efb33b56a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899148089 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.kmac_test_vectors_kmac.2899148089 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1779792408 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1512460317 ps |
| CPU time | 4.64 seconds |
| Started | May 26 03:02:22 PM PDT 24 |
| Finished | May 26 03:02:27 PM PDT 24 |
| Peak memory | 215564 kb |
| Host | smart-33586f2c-1f61-4736-b91b-db01770f6d1c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779792408 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1779792408 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/48.kmac_test_vectors_sha3_224.2802943294 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 100860662440 ps |
| CPU time | 1967.25 seconds |
| Started | May 26 03:02:01 PM PDT 24 |
| Finished | May 26 03:34:50 PM PDT 24 |
| Peak memory | 390904 kb |
| Host | smart-74c03610-8d13-44af-be7f-040bf8dc52bd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2802943294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.2802943294 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/48.kmac_test_vectors_sha3_256.1224733833 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 18800452755 ps |
| CPU time | 1558.53 seconds |
| Started | May 26 03:02:01 PM PDT 24 |
| Finished | May 26 03:28:01 PM PDT 24 |
| Peak memory | 372608 kb |
| Host | smart-4e731e82-39cf-48b2-a925-aee1660a87d0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1224733833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.1224733833 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/48.kmac_test_vectors_sha3_384.315665656 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 28516427850 ps |
| CPU time | 1167.64 seconds |
| Started | May 26 03:02:00 PM PDT 24 |
| Finished | May 26 03:21:28 PM PDT 24 |
| Peak memory | 335788 kb |
| Host | smart-6265342a-9f35-4085-8dcf-357a2e22c545 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=315665656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.315665656 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/48.kmac_test_vectors_sha3_512.2471334531 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 51818419435 ps |
| CPU time | 1030.83 seconds |
| Started | May 26 03:02:01 PM PDT 24 |
| Finished | May 26 03:19:13 PM PDT 24 |
| Peak memory | 300172 kb |
| Host | smart-6d728da1-8ae3-4b60-9392-1f934ce8e5b5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2471334531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.2471334531 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/48.kmac_test_vectors_shake_128.2883684649 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 208954388775 ps |
| CPU time | 4306.42 seconds |
| Started | May 26 03:02:19 PM PDT 24 |
| Finished | May 26 04:14:07 PM PDT 24 |
| Peak memory | 635016 kb |
| Host | smart-06c76355-4500-4045-9c21-b7b25d08ad9e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2883684649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.2883684649 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/48.kmac_test_vectors_shake_256.3555537949 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 218965667964 ps |
| CPU time | 4598.8 seconds |
| Started | May 26 03:02:24 PM PDT 24 |
| Finished | May 26 04:19:04 PM PDT 24 |
| Peak memory | 569904 kb |
| Host | smart-b7021d99-7785-45f7-b9dd-3b12551f021d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3555537949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3555537949 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/48.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/49.kmac_alert_test.3272899622 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 52866538 ps |
| CPU time | 0.79 seconds |
| Started | May 26 03:02:30 PM PDT 24 |
| Finished | May 26 03:02:31 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-901727f3-ca3c-4bd3-a48c-be89411216a1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272899622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3272899622 +enable _masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/49.kmac_app.3524724866 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 6101765730 ps |
| CPU time | 136.75 seconds |
| Started | May 26 03:02:31 PM PDT 24 |
| Finished | May 26 03:04:48 PM PDT 24 |
| Peak memory | 233184 kb |
| Host | smart-aa384192-5580-47ec-8391-85bdcfdec336 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524724866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3524724866 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_app/latest |
| Test location | /workspace/coverage/default/49.kmac_burst_write.2363900197 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 85395547858 ps |
| CPU time | 448.78 seconds |
| Started | May 26 03:02:23 PM PDT 24 |
| Finished | May 26 03:09:52 PM PDT 24 |
| Peak memory | 229652 kb |
| Host | smart-928567e4-b2b7-448f-934d-a068b666ec25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363900197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.2363900197 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/49.kmac_entropy_refresh.104442905 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1956014822 ps |
| CPU time | 51.64 seconds |
| Started | May 26 03:02:29 PM PDT 24 |
| Finished | May 26 03:03:22 PM PDT 24 |
| Peak memory | 223652 kb |
| Host | smart-772218bb-f13b-4cd0-b307-840505058c63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104442905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.104442905 +enable_masking=0 +sw _key_masked=0 |
| Directory | /workspace/49.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/49.kmac_error.4141721844 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 862079824 ps |
| CPU time | 59.67 seconds |
| Started | May 26 03:02:33 PM PDT 24 |
| Finished | May 26 03:03:33 PM PDT 24 |
| Peak memory | 240032 kb |
| Host | smart-a4ecb484-f778-483f-8b86-47ca967c5d85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141721844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.4141721844 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_error/latest |
| Test location | /workspace/coverage/default/49.kmac_key_error.2196731518 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2226800251 ps |
| CPU time | 6.53 seconds |
| Started | May 26 03:02:29 PM PDT 24 |
| Finished | May 26 03:02:36 PM PDT 24 |
| Peak memory | 207192 kb |
| Host | smart-eda2ffdd-aabd-4dba-b7a2-a88d0e05b589 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196731518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2196731518 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_key_error/latest |
| Test location | /workspace/coverage/default/49.kmac_lc_escalation.3893120299 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1972128581 ps |
| CPU time | 22.9 seconds |
| Started | May 26 03:02:29 PM PDT 24 |
| Finished | May 26 03:02:52 PM PDT 24 |
| Peak memory | 227300 kb |
| Host | smart-2d5a4178-1f94-4ab2-9929-0b926fb40936 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893120299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3893120299 +enable_masking=0 +sw_k ey_masked=0 |
| Directory | /workspace/49.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/49.kmac_long_msg_and_output.1055167052 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 8270873724 ps |
| CPU time | 239.71 seconds |
| Started | May 26 03:02:24 PM PDT 24 |
| Finished | May 26 03:06:25 PM PDT 24 |
| Peak memory | 241008 kb |
| Host | smart-ab018262-bf11-437e-805f-9c2ccb49c881 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055167052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a nd_output.1055167052 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/49.kmac_sideload.1399315527 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 10884094325 ps |
| CPU time | 124.72 seconds |
| Started | May 26 03:02:23 PM PDT 24 |
| Finished | May 26 03:04:29 PM PDT 24 |
| Peak memory | 228520 kb |
| Host | smart-7244bde0-12bb-4f4c-8074-c06ad4a79ef3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399315527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1399315527 +e nable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_sideload/latest |
| Test location | /workspace/coverage/default/49.kmac_smoke.1837715957 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 6359116976 ps |
| CPU time | 14.19 seconds |
| Started | May 26 03:02:21 PM PDT 24 |
| Finished | May 26 03:02:36 PM PDT 24 |
| Peak memory | 219208 kb |
| Host | smart-751f69ef-8f35-48b1-9cd5-56571df0e4ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837715957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1837715957 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_smoke/latest |
| Test location | /workspace/coverage/default/49.kmac_stress_all.939575304 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 20754092868 ps |
| CPU time | 226.12 seconds |
| Started | May 26 03:02:29 PM PDT 24 |
| Finished | May 26 03:06:16 PM PDT 24 |
| Peak memory | 269972 kb |
| Host | smart-62533a73-2bdb-4035-8541-5c2ea7962119 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=939575304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.939575304 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/49.kmac_test_vectors_kmac.3606286483 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 751643808 ps |
| CPU time | 4.96 seconds |
| Started | May 26 03:02:32 PM PDT 24 |
| Finished | May 26 03:02:38 PM PDT 24 |
| Peak memory | 215548 kb |
| Host | smart-ec49d29f-a13c-4d89-97a2-58c27facaa7b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606286483 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.kmac_test_vectors_kmac.3606286483 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.214675721 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 127582622 ps |
| CPU time | 4.23 seconds |
| Started | May 26 03:02:29 PM PDT 24 |
| Finished | May 26 03:02:34 PM PDT 24 |
| Peak memory | 215576 kb |
| Host | smart-91b2995a-d48d-4f3a-890f-2829cad2c236 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214675721 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 49.kmac_test_vectors_kmac_xof.214675721 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1189831205 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 423491287097 ps |
| CPU time | 1938.4 seconds |
| Started | May 26 03:02:23 PM PDT 24 |
| Finished | May 26 03:34:42 PM PDT 24 |
| Peak memory | 376824 kb |
| Host | smart-a16d449f-3803-43f4-b779-f7fedc49e6bb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1189831205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1189831205 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/49.kmac_test_vectors_sha3_256.3981471628 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 63794645176 ps |
| CPU time | 1748.6 seconds |
| Started | May 26 03:02:29 PM PDT 24 |
| Finished | May 26 03:31:39 PM PDT 24 |
| Peak memory | 374428 kb |
| Host | smart-f26a26d6-36c1-4b12-9293-1c268edbd57b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3981471628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.3981471628 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/49.kmac_test_vectors_sha3_384.164064961 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 48714336140 ps |
| CPU time | 1306.08 seconds |
| Started | May 26 03:02:33 PM PDT 24 |
| Finished | May 26 03:24:20 PM PDT 24 |
| Peak memory | 330468 kb |
| Host | smart-e1a2556c-4dba-4be2-b21b-5b795cb51aab |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=164064961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.164064961 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/49.kmac_test_vectors_sha3_512.2644407314 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 40101106473 ps |
| CPU time | 757.17 seconds |
| Started | May 26 03:02:30 PM PDT 24 |
| Finished | May 26 03:15:08 PM PDT 24 |
| Peak memory | 296056 kb |
| Host | smart-e79d3765-d27c-44fe-a9bb-707fa9b25381 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2644407314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.2644407314 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/49.kmac_test_vectors_shake_128.1963183817 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 50886725387 ps |
| CPU time | 4352.86 seconds |
| Started | May 26 03:02:30 PM PDT 24 |
| Finished | May 26 04:15:04 PM PDT 24 |
| Peak memory | 651120 kb |
| Host | smart-620e344e-1013-4e12-a6b3-fb435a71b588 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1963183817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.1963183817 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/49.kmac_test_vectors_shake_256.2367583476 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 897185206624 ps |
| CPU time | 4174.38 seconds |
| Started | May 26 03:02:30 PM PDT 24 |
| Finished | May 26 04:12:05 PM PDT 24 |
| Peak memory | 550804 kb |
| Host | smart-8db5ca61-250e-4386-a200-cdc6d92eb4c4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2367583476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.2367583476 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/49.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/5.kmac_alert_test.1849500390 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 25621326 ps |
| CPU time | 0.78 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 02:55:17 PM PDT 24 |
| Peak memory | 204900 kb |
| Host | smart-14c86edd-eaa6-4a6f-8d46-3f9134131fbb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849500390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1849500390 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/5.kmac_app.4205798955 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 10542302463 ps |
| CPU time | 258.05 seconds |
| Started | May 26 02:55:08 PM PDT 24 |
| Finished | May 26 02:59:28 PM PDT 24 |
| Peak memory | 243472 kb |
| Host | smart-f1a579c9-9c8a-4acc-82c6-10f2584c56cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205798955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.4205798955 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_app/latest |
| Test location | /workspace/coverage/default/5.kmac_app_with_partial_data.2476971380 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 16764125074 ps |
| CPU time | 332.11 seconds |
| Started | May 26 02:55:12 PM PDT 24 |
| Finished | May 26 03:00:53 PM PDT 24 |
| Peak memory | 244692 kb |
| Host | smart-a3e6ae26-c996-486c-b93e-245c1a764f30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476971380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2476971380 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/5.kmac_burst_write.3494257251 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 13371746578 ps |
| CPU time | 99.83 seconds |
| Started | May 26 02:55:10 PM PDT 24 |
| Finished | May 26 02:56:52 PM PDT 24 |
| Peak memory | 223728 kb |
| Host | smart-feeb9919-0132-49e2-a156-e13b9c5319ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494257251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3494257251 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/5.kmac_edn_timeout_error.3132553479 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 17660043 ps |
| CPU time | 1.01 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 02:55:21 PM PDT 24 |
| Peak memory | 215052 kb |
| Host | smart-407b9222-137f-4061-97b3-6d8b88d41247 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3132553479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3132553479 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/5.kmac_entropy_mode_error.3498797910 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1024060842 ps |
| CPU time | 37.66 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 02:55:54 PM PDT 24 |
| Peak memory | 221064 kb |
| Host | smart-f672dd9d-1fef-4a47-92f7-1d5c1728c960 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3498797910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3498797910 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/5.kmac_entropy_ready_error.2083685020 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 4432594916 ps |
| CPU time | 28.5 seconds |
| Started | May 26 02:55:07 PM PDT 24 |
| Finished | May 26 02:55:38 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-924c5983-9c5d-4146-9721-ae8c902c0133 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083685020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2083685020 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/5.kmac_entropy_refresh.2725184877 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 21856489721 ps |
| CPU time | 122.21 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 02:57:22 PM PDT 24 |
| Peak memory | 232512 kb |
| Host | smart-6b6ae7a2-b277-4265-a9c4-44e4b8be9162 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725184877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2725184877 +enable_masking=0 +s w_key_masked=0 |
| Directory | /workspace/5.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/5.kmac_error.3380466815 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 24304636761 ps |
| CPU time | 270.64 seconds |
| Started | May 26 02:55:25 PM PDT 24 |
| Finished | May 26 02:59:57 PM PDT 24 |
| Peak memory | 252736 kb |
| Host | smart-3dc0280d-280a-406b-af28-a457f90c1662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380466815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3380466815 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_error/latest |
| Test location | /workspace/coverage/default/5.kmac_key_error.1671434858 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1529204800 ps |
| CPU time | 2.68 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 02:55:18 PM PDT 24 |
| Peak memory | 207060 kb |
| Host | smart-d5259055-0b90-4052-bea6-7af949bba3fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671434858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1671434858 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_key_error/latest |
| Test location | /workspace/coverage/default/5.kmac_lc_escalation.330070913 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 160486497 ps |
| CPU time | 1.33 seconds |
| Started | May 26 02:55:09 PM PDT 24 |
| Finished | May 26 02:55:12 PM PDT 24 |
| Peak memory | 215592 kb |
| Host | smart-4fdb46f3-cf7f-49ce-bd3d-41489df53a69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330070913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.330070913 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/5.kmac_long_msg_and_output.2561168802 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 63615806662 ps |
| CPU time | 912.61 seconds |
| Started | May 26 02:55:11 PM PDT 24 |
| Finished | May 26 03:10:26 PM PDT 24 |
| Peak memory | 301268 kb |
| Host | smart-de59a0bd-1ccd-4813-8198-87f4b7a53fa6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561168802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an d_output.2561168802 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/5.kmac_mubi.4278142353 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 6440485064 ps |
| CPU time | 41.41 seconds |
| Started | May 26 02:55:05 PM PDT 24 |
| Finished | May 26 02:55:50 PM PDT 24 |
| Peak memory | 224104 kb |
| Host | smart-93bddec2-fe46-4a44-8eda-8665a5b4c98c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278142353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.4278142353 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_mubi/latest |
| Test location | /workspace/coverage/default/5.kmac_sideload.499114381 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 15779143020 ps |
| CPU time | 115.31 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:57:12 PM PDT 24 |
| Peak memory | 230424 kb |
| Host | smart-9b4fe058-1fc3-4d62-84c1-a11180c3df34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499114381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.499114381 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_sideload/latest |
| Test location | /workspace/coverage/default/5.kmac_smoke.3751407806 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 420656376 ps |
| CPU time | 4.67 seconds |
| Started | May 26 02:55:10 PM PDT 24 |
| Finished | May 26 02:55:17 PM PDT 24 |
| Peak memory | 223640 kb |
| Host | smart-2fe25199-73a1-416b-8edd-2c63c45a0675 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751407806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3751407806 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_smoke/latest |
| Test location | /workspace/coverage/default/5.kmac_stress_all.2247290532 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 140996993763 ps |
| CPU time | 506.37 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 03:03:46 PM PDT 24 |
| Peak memory | 290520 kb |
| Host | smart-908c354c-1920-4d40-b638-56a97a1d1f04 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2247290532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2247290532 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/5.kmac_test_vectors_kmac.1543199255 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 522527994 ps |
| CPU time | 4.16 seconds |
| Started | May 26 02:55:08 PM PDT 24 |
| Finished | May 26 02:55:14 PM PDT 24 |
| Peak memory | 215544 kb |
| Host | smart-44b68c01-6460-412a-9a6b-25763c2e3f30 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543199255 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.kmac_test_vectors_kmac.1543199255 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.1111082709 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 1138942395 ps |
| CPU time | 5 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:55:24 PM PDT 24 |
| Peak memory | 215552 kb |
| Host | smart-bc31877d-e4b5-4c10-8c39-f18a6e9a32c0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111082709 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.1111082709 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/5.kmac_test_vectors_sha3_224.2880836607 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 132503977498 ps |
| CPU time | 1753.62 seconds |
| Started | May 26 02:55:06 PM PDT 24 |
| Finished | May 26 03:24:22 PM PDT 24 |
| Peak memory | 392220 kb |
| Host | smart-6a0a329b-ed12-4fc0-a635-b90a8d05fd36 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2880836607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2880836607 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/5.kmac_test_vectors_sha3_256.1338741333 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 18334617736 ps |
| CPU time | 1429.19 seconds |
| Started | May 26 02:55:09 PM PDT 24 |
| Finished | May 26 03:19:00 PM PDT 24 |
| Peak memory | 389244 kb |
| Host | smart-1aa892ae-7b4e-4a69-b530-ab484546b9a2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1338741333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1338741333 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/5.kmac_test_vectors_sha3_384.3761581455 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 34682541981 ps |
| CPU time | 1123.21 seconds |
| Started | May 26 02:55:09 PM PDT 24 |
| Finished | May 26 03:13:54 PM PDT 24 |
| Peak memory | 324684 kb |
| Host | smart-a57bb8bd-035d-4a9c-8852-a92891a08035 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3761581455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3761581455 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/5.kmac_test_vectors_sha3_512.4192472602 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 9716975023 ps |
| CPU time | 747.42 seconds |
| Started | May 26 02:55:08 PM PDT 24 |
| Finished | May 26 03:07:38 PM PDT 24 |
| Peak memory | 290980 kb |
| Host | smart-d8cfaa0c-c8ba-4b1d-912b-87b5740735a3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4192472602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.4192472602 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/5.kmac_test_vectors_shake_128.1942889221 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 179553033934 ps |
| CPU time | 4892.1 seconds |
| Started | May 26 02:55:06 PM PDT 24 |
| Finished | May 26 04:16:42 PM PDT 24 |
| Peak memory | 651916 kb |
| Host | smart-a6904f97-792a-4cdc-9cf5-d3fdea88f4a9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1942889221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.1942889221 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/5.kmac_test_vectors_shake_256.2229654780 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 726898973010 ps |
| CPU time | 3391.45 seconds |
| Started | May 26 02:55:12 PM PDT 24 |
| Finished | May 26 03:51:46 PM PDT 24 |
| Peak memory | 567992 kb |
| Host | smart-3ff55e21-6ec8-4158-a8f2-3c031b83670e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2229654780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.2229654780 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/5.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/6.kmac_alert_test.1776532624 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 36836626 ps |
| CPU time | 0.75 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 02:55:22 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-40724228-509e-464b-a537-5c9dc923060f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776532624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1776532624 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/6.kmac_app.3531072083 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 10017219964 ps |
| CPU time | 35.24 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:55:53 PM PDT 24 |
| Peak memory | 223800 kb |
| Host | smart-dd4d6373-ffab-4539-8894-21b7da66c3b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531072083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3531072083 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_app/latest |
| Test location | /workspace/coverage/default/6.kmac_app_with_partial_data.781979074 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 24167347809 ps |
| CPU time | 258.36 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 02:59:39 PM PDT 24 |
| Peak memory | 240292 kb |
| Host | smart-cb245b62-e19e-4bf0-8e06-b5990fd51a6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781979074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.781979074 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/6.kmac_burst_write.4264944980 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 64246263387 ps |
| CPU time | 489.92 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 03:03:30 PM PDT 24 |
| Peak memory | 229132 kb |
| Host | smart-078fb758-2d18-49b4-99cc-0b3553c8be77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264944980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.4264944980 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/6.kmac_edn_timeout_error.500075972 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 602973354 ps |
| CPU time | 16.39 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:55:33 PM PDT 24 |
| Peak memory | 223956 kb |
| Host | smart-c3ad15b1-0bfc-4dd7-a920-c8cf1c3f995c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=500075972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.500075972 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/6.kmac_entropy_mode_error.865431556 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 204398685 ps |
| CPU time | 14.08 seconds |
| Started | May 26 02:55:24 PM PDT 24 |
| Finished | May 26 02:55:39 PM PDT 24 |
| Peak memory | 216260 kb |
| Host | smart-8c476869-2b9c-4236-af3e-7453a5120f1e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=865431556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.865431556 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/6.kmac_entropy_ready_error.1094858561 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3384009787 ps |
| CPU time | 8.12 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:55:29 PM PDT 24 |
| Peak memory | 215620 kb |
| Host | smart-2a5ab3f6-1cb6-47fd-82f9-346e34f04de8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094858561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1094858561 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/6.kmac_entropy_refresh.3320645575 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2433929342 ps |
| CPU time | 73.94 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 02:56:34 PM PDT 24 |
| Peak memory | 226708 kb |
| Host | smart-6e396c2d-71ca-4f9e-afd4-d9c0f993918f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320645575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3320645575 +enable_masking=0 +s w_key_masked=0 |
| Directory | /workspace/6.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/6.kmac_error.1988346116 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 6314994600 ps |
| CPU time | 62.41 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 02:56:23 PM PDT 24 |
| Peak memory | 240052 kb |
| Host | smart-1ff59679-7df5-494d-83e1-e6e5a1730595 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988346116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1988346116 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_error/latest |
| Test location | /workspace/coverage/default/6.kmac_key_error.426521131 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3027214936 ps |
| CPU time | 6.44 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:55:24 PM PDT 24 |
| Peak memory | 207124 kb |
| Host | smart-f50f5b04-c796-49f9-b5d3-606f9530262f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426521131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.426521131 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_key_error/latest |
| Test location | /workspace/coverage/default/6.kmac_lc_escalation.1320818740 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 40605987 ps |
| CPU time | 1.26 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 02:55:22 PM PDT 24 |
| Peak memory | 215344 kb |
| Host | smart-253b61e2-40aa-4e33-96ac-20c6d0c51c55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320818740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1320818740 +enable_masking=0 +sw_ke y_masked=0 |
| Directory | /workspace/6.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/6.kmac_long_msg_and_output.3529630524 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 97953778934 ps |
| CPU time | 1436.36 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 03:19:11 PM PDT 24 |
| Peak memory | 353076 kb |
| Host | smart-e39e7f73-ea51-4f89-b923-0259d068bd55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529630524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an d_output.3529630524 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/6.kmac_mubi.2353148177 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 19681290800 ps |
| CPU time | 91.87 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:56:53 PM PDT 24 |
| Peak memory | 227520 kb |
| Host | smart-ffd89ff9-a0c1-4033-8516-d0f02d63ecb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2353148177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2353148177 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_mubi/latest |
| Test location | /workspace/coverage/default/6.kmac_sideload.912640526 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 42068241789 ps |
| CPU time | 274.44 seconds |
| Started | May 26 02:55:12 PM PDT 24 |
| Finished | May 26 02:59:48 PM PDT 24 |
| Peak memory | 242940 kb |
| Host | smart-b94d8004-fe5e-4e49-9077-a09b673c0370 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912640526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.912640526 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_sideload/latest |
| Test location | /workspace/coverage/default/6.kmac_smoke.964963316 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 5968676197 ps |
| CPU time | 45.78 seconds |
| Started | May 26 02:55:09 PM PDT 24 |
| Finished | May 26 02:55:57 PM PDT 24 |
| Peak memory | 221620 kb |
| Host | smart-ba03d2d7-a2e6-49a2-ab87-6c852b6aade1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964963316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.964963316 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_smoke/latest |
| Test location | /workspace/coverage/default/6.kmac_stress_all.3531581309 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 88346396934 ps |
| CPU time | 1970.63 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 03:28:07 PM PDT 24 |
| Peak memory | 433944 kb |
| Host | smart-e6c65fd0-92e7-461f-8df5-0016aee90709 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3531581309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3531581309 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/6.kmac_test_vectors_kmac.911919694 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 279985189 ps |
| CPU time | 3.94 seconds |
| Started | May 26 02:55:12 PM PDT 24 |
| Finished | May 26 02:55:19 PM PDT 24 |
| Peak memory | 215560 kb |
| Host | smart-f87719ff-5b33-4e87-8fd1-7769e27c4a9c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911919694 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 6.kmac_test_vectors_kmac.911919694 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3154050237 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 71945678 ps |
| CPU time | 3.87 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:55:23 PM PDT 24 |
| Peak memory | 215548 kb |
| Host | smart-8c89e8b9-8924-4391-b216-85c74e2b8f8f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154050237 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3154050237 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/6.kmac_test_vectors_sha3_224.3177316733 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 598894073504 ps |
| CPU time | 2051.41 seconds |
| Started | May 26 02:55:07 PM PDT 24 |
| Finished | May 26 03:29:21 PM PDT 24 |
| Peak memory | 397280 kb |
| Host | smart-7e6b4f47-a02b-4697-8f6a-472d3937b6f5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3177316733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3177316733 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/6.kmac_test_vectors_sha3_256.3368417449 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 18629181472 ps |
| CPU time | 1441.59 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 03:19:21 PM PDT 24 |
| Peak memory | 372932 kb |
| Host | smart-be186e8d-8e67-40ba-a52f-6f05ce6500e1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3368417449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3368417449 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/6.kmac_test_vectors_sha3_384.3514527033 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 488205906668 ps |
| CPU time | 1503.26 seconds |
| Started | May 26 02:55:07 PM PDT 24 |
| Finished | May 26 03:20:13 PM PDT 24 |
| Peak memory | 327680 kb |
| Host | smart-3029c89b-552c-4625-9efa-8ccc8968fc5f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3514527033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.3514527033 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/6.kmac_test_vectors_sha3_512.560124783 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 329049843653 ps |
| CPU time | 966.06 seconds |
| Started | May 26 02:55:12 PM PDT 24 |
| Finished | May 26 03:11:21 PM PDT 24 |
| Peak memory | 296584 kb |
| Host | smart-3bc15565-c965-4530-82c0-32b229cc2244 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=560124783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.560124783 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/6.kmac_test_vectors_shake_128.2489274095 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 711200424867 ps |
| CPU time | 5037.72 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 04:19:16 PM PDT 24 |
| Peak memory | 642464 kb |
| Host | smart-25eb3822-bb6f-46cd-8a1b-3f3153ac998b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2489274095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.2489274095 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/6.kmac_test_vectors_shake_256.545826822 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 43649763311 ps |
| CPU time | 3231.91 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 03:49:12 PM PDT 24 |
| Peak memory | 559940 kb |
| Host | smart-3672d456-3fac-4b37-9f97-3af02fdeb0c0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=545826822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.545826822 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/6.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/7.kmac_alert_test.1786356992 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 17803522 ps |
| CPU time | 0.78 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:55:18 PM PDT 24 |
| Peak memory | 204840 kb |
| Host | smart-1de503e0-66a2-4f03-a7ba-f65d9f662281 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786356992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1786356992 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/7.kmac_app.21447746 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 11262718838 ps |
| CPU time | 204.69 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 02:58:45 PM PDT 24 |
| Peak memory | 240072 kb |
| Host | smart-33071429-1514-447e-bb94-90b1dc98ae0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21447746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.21447746 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_app/latest |
| Test location | /workspace/coverage/default/7.kmac_app_with_partial_data.2005098236 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 25704080347 ps |
| CPU time | 288.83 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 03:00:05 PM PDT 24 |
| Peak memory | 246160 kb |
| Host | smart-a4753347-984a-4d4d-a4f0-aef8b291bde1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005098236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2005098236 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/7.kmac_burst_write.753298568 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 164542980850 ps |
| CPU time | 703.21 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 03:07:05 PM PDT 24 |
| Peak memory | 229776 kb |
| Host | smart-92e3c7f1-51ed-480b-86b4-9892cb6af3e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753298568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.753298568 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/7.kmac_edn_timeout_error.1454112307 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 283078010 ps |
| CPU time | 16.83 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:55:36 PM PDT 24 |
| Peak memory | 224120 kb |
| Host | smart-6f81ae28-0938-4847-b801-d57e9b210040 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1454112307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1454112307 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/7.kmac_entropy_mode_error.2139257869 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1500768763 ps |
| CPU time | 28.24 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:55:45 PM PDT 24 |
| Peak memory | 223384 kb |
| Host | smart-17c7aa5d-ad7d-471f-973c-4dd440c7e8ec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2139257869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2139257869 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/7.kmac_entropy_ready_error.2805401167 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4220460421 ps |
| CPU time | 10.9 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 02:55:31 PM PDT 24 |
| Peak memory | 223708 kb |
| Host | smart-27f1bffd-c9c1-4fb3-a8a3-0dfe58b46379 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805401167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2805401167 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/7.kmac_entropy_refresh.2990306200 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2607409630 ps |
| CPU time | 3.49 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:55:22 PM PDT 24 |
| Peak memory | 215552 kb |
| Host | smart-201f272c-4b24-4780-a310-82f5ec4b855a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990306200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2990306200 +enable_masking=0 +s w_key_masked=0 |
| Directory | /workspace/7.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/7.kmac_error.3785963729 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 79357692633 ps |
| CPU time | 338.66 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 03:00:55 PM PDT 24 |
| Peak memory | 255800 kb |
| Host | smart-8a81d6b2-7449-4ac2-b5ef-4826e600f891 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785963729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3785963729 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_error/latest |
| Test location | /workspace/coverage/default/7.kmac_key_error.1795541312 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 998792718 ps |
| CPU time | 5.06 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 02:55:26 PM PDT 24 |
| Peak memory | 215304 kb |
| Host | smart-8e23ddde-e2a9-402d-9093-de361051d262 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795541312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1795541312 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_key_error/latest |
| Test location | /workspace/coverage/default/7.kmac_lc_escalation.320742284 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 71848293 ps |
| CPU time | 1.33 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:55:18 PM PDT 24 |
| Peak memory | 219268 kb |
| Host | smart-b0bb340a-f0ee-4ed4-8510-7c2c847d5ff6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320742284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.320742284 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/7.kmac_long_msg_and_output.2357010265 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 87833602040 ps |
| CPU time | 1304.98 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 03:17:02 PM PDT 24 |
| Peak memory | 344828 kb |
| Host | smart-84bd3f9e-bbba-4002-9de3-37653f58ec4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357010265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.2357010265 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/7.kmac_mubi.67685457 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 30032354673 ps |
| CPU time | 289.19 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 03:00:07 PM PDT 24 |
| Peak memory | 246308 kb |
| Host | smart-7789dd5e-66b5-41e5-a470-070ca864054b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67685457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.67685457 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_mubi/latest |
| Test location | /workspace/coverage/default/7.kmac_sideload.1178729396 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 4563448188 ps |
| CPU time | 28.78 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:55:51 PM PDT 24 |
| Peak memory | 219468 kb |
| Host | smart-360f4d3d-3163-4f17-942c-96e30b32e5e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178729396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1178729396 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_sideload/latest |
| Test location | /workspace/coverage/default/7.kmac_smoke.2018772369 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 3828155973 ps |
| CPU time | 51.07 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 02:56:12 PM PDT 24 |
| Peak memory | 217304 kb |
| Host | smart-f06dda5c-1fc9-4bf8-b667-40aabe085905 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018772369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2018772369 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_smoke/latest |
| Test location | /workspace/coverage/default/7.kmac_stress_all.3677643915 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 15105415680 ps |
| CPU time | 703.17 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 03:07:04 PM PDT 24 |
| Peak memory | 317432 kb |
| Host | smart-d37225a8-8fe4-4501-a267-b19ef93cb929 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3677643915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3677643915 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/7.kmac_test_vectors_kmac.2052136727 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 124012209 ps |
| CPU time | 4.15 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 02:55:25 PM PDT 24 |
| Peak memory | 215568 kb |
| Host | smart-9896c5f2-b41c-475c-9637-b9167221bc42 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052136727 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.kmac_test_vectors_kmac.2052136727 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2848649437 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 121702032 ps |
| CPU time | 3.98 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 02:55:24 PM PDT 24 |
| Peak memory | 215552 kb |
| Host | smart-d6cd7acb-3391-493c-aeb9-cb555777ddd2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848649437 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2848649437 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/7.kmac_test_vectors_sha3_224.3630077647 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 71799317889 ps |
| CPU time | 1506.51 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 03:20:27 PM PDT 24 |
| Peak memory | 388016 kb |
| Host | smart-fa0d2039-ec30-47c6-b9c7-d303f5f882ae |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3630077647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.3630077647 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/7.kmac_test_vectors_sha3_256.2347052578 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 67615875481 ps |
| CPU time | 1494.85 seconds |
| Started | May 26 02:55:12 PM PDT 24 |
| Finished | May 26 03:20:09 PM PDT 24 |
| Peak memory | 371260 kb |
| Host | smart-53f87615-1f64-4294-94d0-56129f96e6d2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2347052578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.2347052578 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/7.kmac_test_vectors_sha3_384.2777088945 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 50835647923 ps |
| CPU time | 1291.77 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 03:16:51 PM PDT 24 |
| Peak memory | 336896 kb |
| Host | smart-227f81a2-c8eb-4a71-bfcc-95c1bbaf01b9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2777088945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.2777088945 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/7.kmac_test_vectors_sha3_512.73517257 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 33702036513 ps |
| CPU time | 925.05 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 03:10:45 PM PDT 24 |
| Peak memory | 293152 kb |
| Host | smart-29d62389-df9f-4e63-8836-9ab962d75931 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=73517257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.73517257 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/7.kmac_test_vectors_shake_128.3290890541 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 258134665966 ps |
| CPU time | 5412.64 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 04:25:32 PM PDT 24 |
| Peak memory | 654952 kb |
| Host | smart-66df9010-d4da-4809-8abb-527898a867f1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3290890541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.3290890541 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/7.kmac_test_vectors_shake_256.2604250926 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 846828979797 ps |
| CPU time | 4388.4 seconds |
| Started | May 26 02:55:21 PM PDT 24 |
| Finished | May 26 04:08:32 PM PDT 24 |
| Peak memory | 541852 kb |
| Host | smart-69315f26-fd7a-4065-9623-dcdab1930a72 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2604250926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2604250926 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/7.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/8.kmac_alert_test.4078433983 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 59042067 ps |
| CPU time | 0.79 seconds |
| Started | May 26 02:55:29 PM PDT 24 |
| Finished | May 26 02:55:31 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-7956b2db-f585-476f-8c25-506f0e066529 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078433983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.4078433983 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/8.kmac_app.3297224954 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 49694492328 ps |
| CPU time | 236.58 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 02:59:14 PM PDT 24 |
| Peak memory | 241656 kb |
| Host | smart-8908533d-2d0f-4cbe-8844-ef7fac549f02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297224954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3297224954 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_app/latest |
| Test location | /workspace/coverage/default/8.kmac_app_with_partial_data.813235411 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5029756136 ps |
| CPU time | 243.65 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:59:22 PM PDT 24 |
| Peak memory | 245076 kb |
| Host | smart-7fb35b94-3f71-43cd-8019-28025e18b0d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813235411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.813235411 +enable_ma sking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/8.kmac_burst_write.2172656186 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3319457062 ps |
| CPU time | 265.02 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:59:47 PM PDT 24 |
| Peak memory | 226548 kb |
| Host | smart-b6ac419d-7c83-4af7-bc7c-50626af3db77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172656186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2172656186 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/8.kmac_edn_timeout_error.3628662828 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 6232049426 ps |
| CPU time | 32.38 seconds |
| Started | May 26 02:55:24 PM PDT 24 |
| Finished | May 26 02:55:58 PM PDT 24 |
| Peak memory | 219636 kb |
| Host | smart-08c754f5-15e8-4f95-917e-cde37d24a837 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3628662828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3628662828 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/8.kmac_entropy_mode_error.4198574009 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 384080378 ps |
| CPU time | 24.59 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:55:46 PM PDT 24 |
| Peak memory | 219760 kb |
| Host | smart-1973dced-aa2b-4f68-b8c8-307883a5d612 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4198574009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.4198574009 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/8.kmac_entropy_ready_error.2653080262 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2732265630 ps |
| CPU time | 29.87 seconds |
| Started | May 26 02:55:34 PM PDT 24 |
| Finished | May 26 02:56:05 PM PDT 24 |
| Peak memory | 215632 kb |
| Host | smart-b3e07bd6-678b-48f6-bab0-d84303f1ab11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653080262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2653080262 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/8.kmac_entropy_refresh.24122399 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 25037658570 ps |
| CPU time | 57.44 seconds |
| Started | May 26 02:55:21 PM PDT 24 |
| Finished | May 26 02:56:20 PM PDT 24 |
| Peak memory | 223296 kb |
| Host | smart-2e2bd448-bd5d-40bb-b3fa-12c81a956f40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24122399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.24122399 +enable_masking=0 +sw_ke y_masked=0 |
| Directory | /workspace/8.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/8.kmac_error.2058701176 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1699169585 ps |
| CPU time | 117.25 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:57:19 PM PDT 24 |
| Peak memory | 240392 kb |
| Host | smart-04e31a26-5ca1-4f26-83c5-774bfd108cde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058701176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2058701176 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_error/latest |
| Test location | /workspace/coverage/default/8.kmac_key_error.294981376 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 1719521455 ps |
| CPU time | 4.9 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:55:27 PM PDT 24 |
| Peak memory | 207168 kb |
| Host | smart-c3cedc3d-06b2-4aa9-a51d-b325b8d02f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294981376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.294981376 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_key_error/latest |
| Test location | /workspace/coverage/default/8.kmac_lc_escalation.773724386 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 128333715 ps |
| CPU time | 1.15 seconds |
| Started | May 26 02:55:28 PM PDT 24 |
| Finished | May 26 02:55:31 PM PDT 24 |
| Peak memory | 215284 kb |
| Host | smart-a525dd32-7318-439e-920e-d5ea92e8f9f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773724386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.773724386 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/8.kmac_long_msg_and_output.320215609 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 146476440845 ps |
| CPU time | 827.68 seconds |
| Started | May 26 02:55:12 PM PDT 24 |
| Finished | May 26 03:09:02 PM PDT 24 |
| Peak memory | 292032 kb |
| Host | smart-08eedad8-b49d-4de3-95be-3af2ca81b801 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320215609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and _output.320215609 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/8.kmac_mubi.3520433663 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2529878454 ps |
| CPU time | 60.98 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:56:20 PM PDT 24 |
| Peak memory | 224436 kb |
| Host | smart-e00c4d4e-f5c9-41bb-84ee-ff8d78b2dea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520433663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3520433663 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_mubi/latest |
| Test location | /workspace/coverage/default/8.kmac_sideload.939580791 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 9553329751 ps |
| CPU time | 33.07 seconds |
| Started | May 26 02:55:17 PM PDT 24 |
| Finished | May 26 02:55:54 PM PDT 24 |
| Peak memory | 219832 kb |
| Host | smart-6658408e-6f33-455a-8d44-4cea6ce03a3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939580791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.939580791 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_sideload/latest |
| Test location | /workspace/coverage/default/8.kmac_smoke.2804943268 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3196572911 ps |
| CPU time | 39.4 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:56:01 PM PDT 24 |
| Peak memory | 217016 kb |
| Host | smart-1cf0c95a-9b75-416d-9bd2-d970f33039b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804943268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2804943268 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_smoke/latest |
| Test location | /workspace/coverage/default/8.kmac_stress_all.224901925 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 27993911153 ps |
| CPU time | 1985.46 seconds |
| Started | May 26 02:55:24 PM PDT 24 |
| Finished | May 26 03:28:31 PM PDT 24 |
| Peak memory | 453704 kb |
| Host | smart-7cac9809-6bd2-43b4-b29c-d70b6ebaaeb2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=224901925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.224901925 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/8.kmac_test_vectors_kmac.1598730846 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 169941652 ps |
| CPU time | 4.15 seconds |
| Started | May 26 02:55:18 PM PDT 24 |
| Finished | May 26 02:55:26 PM PDT 24 |
| Peak memory | 215536 kb |
| Host | smart-3ec16c96-f617-4e7d-b3bc-6cf28e47d217 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598730846 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.kmac_test_vectors_kmac.1598730846 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.3769545465 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 167214929 ps |
| CPU time | 4.57 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 02:55:24 PM PDT 24 |
| Peak memory | 215516 kb |
| Host | smart-c3a851ff-c4fc-4f7d-80e8-19747bc243a9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769545465 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.3769545465 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/8.kmac_test_vectors_sha3_224.3532449803 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 357815050493 ps |
| CPU time | 1932.62 seconds |
| Started | May 26 02:55:19 PM PDT 24 |
| Finished | May 26 03:27:35 PM PDT 24 |
| Peak memory | 398900 kb |
| Host | smart-12db3ae4-9045-40d2-9a80-6d6b03f24280 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3532449803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.3532449803 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/8.kmac_test_vectors_sha3_256.341171342 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 313913523325 ps |
| CPU time | 1729.45 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 03:24:05 PM PDT 24 |
| Peak memory | 370476 kb |
| Host | smart-6d091dfb-d9a4-414d-a842-7815e34ee669 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=341171342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.341171342 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/8.kmac_test_vectors_sha3_384.3502161177 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 103477740287 ps |
| CPU time | 1129.66 seconds |
| Started | May 26 02:55:13 PM PDT 24 |
| Finished | May 26 03:14:05 PM PDT 24 |
| Peak memory | 331276 kb |
| Host | smart-5954dd5c-448a-4021-9d8f-f29befceaba4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3502161177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.3502161177 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/8.kmac_test_vectors_sha3_512.2149475852 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 9502532837 ps |
| CPU time | 774.18 seconds |
| Started | May 26 02:55:14 PM PDT 24 |
| Finished | May 26 03:08:12 PM PDT 24 |
| Peak memory | 293244 kb |
| Host | smart-330ff3a1-e5c6-4d0d-81fc-8ab2bfa5d6c7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2149475852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.2149475852 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/8.kmac_test_vectors_shake_128.2130978073 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 221784344590 ps |
| CPU time | 5137.45 seconds |
| Started | May 26 02:55:16 PM PDT 24 |
| Finished | May 26 04:20:58 PM PDT 24 |
| Peak memory | 645712 kb |
| Host | smart-1eec2fb6-94c1-473a-8b95-ad2eef77751c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2130978073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.2130978073 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_test_vectors_shake_128/latest |
| Test location | /workspace/coverage/default/8.kmac_test_vectors_shake_256.149508649 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 299090103422 ps |
| CPU time | 4192.37 seconds |
| Started | May 26 02:55:15 PM PDT 24 |
| Finished | May 26 04:05:12 PM PDT 24 |
| Peak memory | 552732 kb |
| Host | smart-ef524cad-2e0e-4b13-825a-b3a65edfca6d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=149508649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.149508649 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/8.kmac_test_vectors_shake_256/latest |
| Test location | /workspace/coverage/default/9.kmac_alert_test.2135306057 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 28439183 ps |
| CPU time | 0.86 seconds |
| Started | May 26 02:55:22 PM PDT 24 |
| Finished | May 26 02:55:24 PM PDT 24 |
| Peak memory | 204828 kb |
| Host | smart-b08bd3ed-c9bd-49e0-ad3e-4dd4ac632ac4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135306057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2135306057 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_alert_test/latest |
| Test location | /workspace/coverage/default/9.kmac_app.1813465051 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 12012408797 ps |
| CPU time | 243.13 seconds |
| Started | May 26 02:55:23 PM PDT 24 |
| Finished | May 26 02:59:28 PM PDT 24 |
| Peak memory | 242540 kb |
| Host | smart-081b1118-e6e5-4429-bc96-6dc0a0f4e6ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813465051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1813465051 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_app/latest |
| Test location | /workspace/coverage/default/9.kmac_app_with_partial_data.1481639698 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 32765518604 ps |
| CPU time | 264.87 seconds |
| Started | May 26 02:55:38 PM PDT 24 |
| Finished | May 26 03:00:05 PM PDT 24 |
| Peak memory | 243880 kb |
| Host | smart-fec3f606-2bd9-43ea-8b9d-18bc9d4a6bf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481639698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1481639698 +enable_ masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_app_with_partial_data/latest |
| Test location | /workspace/coverage/default/9.kmac_burst_write.4191633311 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 9316994487 ps |
| CPU time | 61.26 seconds |
| Started | May 26 02:55:24 PM PDT 24 |
| Finished | May 26 02:56:27 PM PDT 24 |
| Peak memory | 219304 kb |
| Host | smart-05f299b9-30ad-4a27-bcc1-bc49ebf27fb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191633311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.4191633311 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_burst_write/latest |
| Test location | /workspace/coverage/default/9.kmac_edn_timeout_error.3059846161 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 1741074838 ps |
| CPU time | 8.8 seconds |
| Started | May 26 02:55:22 PM PDT 24 |
| Finished | May 26 02:55:32 PM PDT 24 |
| Peak memory | 215396 kb |
| Host | smart-f3cd1260-e949-44ca-9541-c2c1d4cc91d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3059846161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3059846161 +enabl e_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_edn_timeout_error/latest |
| Test location | /workspace/coverage/default/9.kmac_entropy_mode_error.2894807877 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3687775594 ps |
| CPU time | 15.54 seconds |
| Started | May 26 02:55:32 PM PDT 24 |
| Finished | May 26 02:55:49 PM PDT 24 |
| Peak memory | 223500 kb |
| Host | smart-932fc526-408d-49c8-ac17-fabaada1df85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2894807877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2894807877 +ena ble_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_entropy_mode_error/latest |
| Test location | /workspace/coverage/default/9.kmac_entropy_ready_error.2760624401 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 45510386764 ps |
| CPU time | 55.39 seconds |
| Started | May 26 02:55:21 PM PDT 24 |
| Finished | May 26 02:56:19 PM PDT 24 |
| Peak memory | 215552 kb |
| Host | smart-e61225c2-7fe8-4763-96ff-06f5c44dd9fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760624401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2760624401 +enable_mask ing=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_entropy_ready_error/latest |
| Test location | /workspace/coverage/default/9.kmac_entropy_refresh.2626637201 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 100361655294 ps |
| CPU time | 319.54 seconds |
| Started | May 26 02:55:19 PM PDT 24 |
| Finished | May 26 03:00:42 PM PDT 24 |
| Peak memory | 245728 kb |
| Host | smart-6863a915-311d-4d7e-a5d0-8ee2296409e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626637201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2626637201 +enable_masking=0 +s w_key_masked=0 |
| Directory | /workspace/9.kmac_entropy_refresh/latest |
| Test location | /workspace/coverage/default/9.kmac_error.586437463 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 372604052 ps |
| CPU time | 4.51 seconds |
| Started | May 26 02:55:21 PM PDT 24 |
| Finished | May 26 02:55:27 PM PDT 24 |
| Peak memory | 220872 kb |
| Host | smart-6b1d10f6-dd56-47ea-b244-4795be661826 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586437463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.586437463 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_error/latest |
| Test location | /workspace/coverage/default/9.kmac_key_error.3221076550 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2279499866 ps |
| CPU time | 5.73 seconds |
| Started | May 26 02:55:22 PM PDT 24 |
| Finished | May 26 02:55:29 PM PDT 24 |
| Peak memory | 215288 kb |
| Host | smart-b17556a4-5007-4d0d-a227-ee4d31cdbd22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221076550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3221076550 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_key_error/latest |
| Test location | /workspace/coverage/default/9.kmac_lc_escalation.3055707946 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 63716106 ps |
| CPU time | 1.27 seconds |
| Started | May 26 02:55:22 PM PDT 24 |
| Finished | May 26 02:55:25 PM PDT 24 |
| Peak memory | 216272 kb |
| Host | smart-a0f02d9f-b2a8-48ee-a7c9-733f7d608442 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055707946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3055707946 +enable_masking=0 +sw_ke y_masked=0 |
| Directory | /workspace/9.kmac_lc_escalation/latest |
| Test location | /workspace/coverage/default/9.kmac_long_msg_and_output.480785860 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 97742787285 ps |
| CPU time | 2818.27 seconds |
| Started | May 26 02:55:23 PM PDT 24 |
| Finished | May 26 03:42:23 PM PDT 24 |
| Peak memory | 494020 kb |
| Host | smart-938a8d16-cba7-45ec-bc73-51da27df1728 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480785860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and _output.480785860 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_long_msg_and_output/latest |
| Test location | /workspace/coverage/default/9.kmac_mubi.198897927 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 428719346 ps |
| CPU time | 4.6 seconds |
| Started | May 26 02:55:27 PM PDT 24 |
| Finished | May 26 02:55:32 PM PDT 24 |
| Peak memory | 217212 kb |
| Host | smart-983cfa75-5518-4276-accf-4b447698a650 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198897927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.198897927 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_mubi/latest |
| Test location | /workspace/coverage/default/9.kmac_sideload.2491427241 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 8821207972 ps |
| CPU time | 66.83 seconds |
| Started | May 26 02:55:36 PM PDT 24 |
| Finished | May 26 02:56:44 PM PDT 24 |
| Peak memory | 224800 kb |
| Host | smart-704c3dfc-9644-4052-ab86-ec55d7f1836d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491427241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2491427241 +en able_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_sideload/latest |
| Test location | /workspace/coverage/default/9.kmac_smoke.1858587805 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 7629597553 ps |
| CPU time | 34.6 seconds |
| Started | May 26 02:55:32 PM PDT 24 |
| Finished | May 26 02:56:08 PM PDT 24 |
| Peak memory | 215924 kb |
| Host | smart-7c0e4089-ea70-4b07-b083-17e42e207a49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858587805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1858587805 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_smoke/latest |
| Test location | /workspace/coverage/default/9.kmac_stress_all.3242118494 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 42980631835 ps |
| CPU time | 307.58 seconds |
| Started | May 26 02:55:22 PM PDT 24 |
| Finished | May 26 03:00:31 PM PDT 24 |
| Peak memory | 286720 kb |
| Host | smart-2abba989-e010-4765-b32f-312dc03ee992 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3242118494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3242118494 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_stress_all/latest |
| Test location | /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.121990518 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 192470640036 ps |
| CPU time | 1688.77 seconds |
| Started | May 26 02:55:21 PM PDT 24 |
| Finished | May 26 03:23:32 PM PDT 24 |
| Peak memory | 386988 kb |
| Host | smart-3b882ac1-8a4f-4aa4-9049-a2f7e666f64d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=121990518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.121990518 +enab le_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.kmac_test_vectors_kmac.394447643 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 183193654 ps |
| CPU time | 4.69 seconds |
| Started | May 26 02:55:26 PM PDT 24 |
| Finished | May 26 02:55:31 PM PDT 24 |
| Peak memory | 215508 kb |
| Host | smart-2081a2bb-708b-44e5-aebb-64cc09736124 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394447643 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.kmac_test_vectors_kmac.394447643 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_test_vectors_kmac/latest |
| Test location | /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.4291487548 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 691764771 ps |
| CPU time | 4.64 seconds |
| Started | May 26 02:55:23 PM PDT 24 |
| Finished | May 26 02:55:30 PM PDT 24 |
| Peak memory | 215524 kb |
| Host | smart-67b4fc0d-9d86-4caa-8059-58f132d4e3ee |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291487548 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.4291487548 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspace/coverage/default/9.kmac_test_vectors_sha3_224.3515070158 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 19037320525 ps |
| CPU time | 1532.83 seconds |
| Started | May 26 02:55:24 PM PDT 24 |
| Finished | May 26 03:20:59 PM PDT 24 |
| Peak memory | 396228 kb |
| Host | smart-d96b2618-4700-4b6e-8f3c-a4796180ae97 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3515070158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.3515070158 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_test_vectors_sha3_224/latest |
| Test location | /workspace/coverage/default/9.kmac_test_vectors_sha3_256.3201890769 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 373690130383 ps |
| CPU time | 1826.86 seconds |
| Started | May 26 02:55:32 PM PDT 24 |
| Finished | May 26 03:26:00 PM PDT 24 |
| Peak memory | 366420 kb |
| Host | smart-2ae7cdad-d333-4ee4-abb3-09fe43f144ee |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3201890769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.3201890769 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_test_vectors_sha3_256/latest |
| Test location | /workspace/coverage/default/9.kmac_test_vectors_sha3_384.150328978 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 97877111457 ps |
| CPU time | 1322.23 seconds |
| Started | May 26 02:55:26 PM PDT 24 |
| Finished | May 26 03:17:30 PM PDT 24 |
| Peak memory | 335268 kb |
| Host | smart-8fe69d07-ddfa-4aee-a1c1-53f41829591e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=150328978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.150328978 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_test_vectors_sha3_384/latest |
| Test location | /workspace/coverage/default/9.kmac_test_vectors_sha3_512.836235763 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 38555458589 ps |
| CPU time | 813.98 seconds |
| Started | May 26 02:55:23 PM PDT 24 |
| Finished | May 26 03:08:59 PM PDT 24 |
| Peak memory | 297560 kb |
| Host | smart-74e4c718-7810-4633-9e56-2cb94d601993 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=836235763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.836235763 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_test_vectors_sha3_512/latest |
| Test location | /workspace/coverage/default/9.kmac_test_vectors_shake_128.1944204079 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2119392947943 ps |
| CPU time | 5874.9 seconds |
| Started | May 26 02:55:34 PM PDT 24 |
| Finished | May 26 04:33:30 PM PDT 24 |
| Peak memory | 636468 kb |
| Host | smart-d9411c61-4211-48ec-9d19-6964fcfff8ce |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1944204079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.1944204079 +enable_masking=0 +sw_key_masked=0 |
| Directory | /workspace/9.kmac_test_vectors_shake_128/latest |
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