Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100697914	1			T1	1		T2	112563		T3	346
all_values[1]	100697914	1			T1	1		T2	112563		T3	346
all_values[2]	100697914	1			T1	1		T2	112563		T3	346

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

514458

1

T1

1

T2

3

T4

83

auto[1]

301579284

1

T1

2

T2

337686

T3

1038

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300562281

1

T1

3

T2

336570

T3

906

auto[1]

1531461

1

T2

1119

T3

132

T4

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	168944	1			T4	77		T13	8		T15	12
all_values[0]	auto[0]	auto[1]	2126	1			T4	6		T13	2		T15	4
all_values[0]	auto[1]	auto[0]	100018483	1			T1	1		T2	112190		T3	302
all_values[0]	auto[1]	auto[1]	508361	1			T2	373		T3	44		T4	9
all_values[1]	auto[0]	auto[0]	173416	1			T1	1		T13	55		T22	84
all_values[1]	auto[0]	auto[1]	1649	1			T13	8		T22	6		T28	2
all_values[1]	auto[1]	auto[0]	100014011	1			T2	112190		T3	302		T4	283
all_values[1]	auto[1]	auto[1]	508838	1			T2	373		T3	44		T4	15
all_values[2]	auto[0]	auto[0]	166844	1			T2	2		T13	94		T14	5
all_values[2]	auto[0]	auto[1]	1479	1			T2	1		T13	10		T14	1
all_values[2]	auto[1]	auto[0]	100020583	1			T1	1		T2	112188		T3	302
all_values[2]	auto[1]	auto[1]	509008	1			T2	372		T3	44		T4	15