Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
414848 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
277766 |
1 |
|
|
T2 |
490 |
|
T3 |
58 |
|
T4 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172993 |
1 |
|
|
T2 |
132 |
|
T3 |
10 |
|
T4 |
2 |
lower_val |
170782 |
1 |
|
|
T2 |
102 |
|
T3 |
18 |
|
T4 |
9 |
zero_val |
1784 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347782 |
1 |
|
|
T2 |
240 |
|
T3 |
34 |
|
T4 |
12 |
lower_val |
344828 |
1 |
|
|
T1 |
2 |
|
T2 |
252 |
|
T3 |
26 |
zero_val |
4 |
1 |
|
|
T140 |
2 |
|
T141 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
6 |
12 |
66.67 |
6 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
* |
[zero_val] |
* |
-- |
-- |
6 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
52475 |
1 |
|
|
T13 |
1 |
|
T14 |
4 |
|
T15 |
53 |
higher_val |
higher_val |
auto[1] |
34823 |
1 |
|
|
T2 |
68 |
|
T3 |
5 |
|
T4 |
2 |
higher_val |
lower_val |
auto[0] |
51374 |
1 |
|
|
T15 |
47 |
|
T16 |
34 |
|
T17 |
572 |
higher_val |
lower_val |
auto[1] |
34321 |
1 |
|
|
T2 |
64 |
|
T3 |
5 |
|
T13 |
61 |
lower_val |
higher_val |
auto[0] |
51283 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T15 |
57 |
lower_val |
higher_val |
auto[1] |
34483 |
1 |
|
|
T2 |
48 |
|
T3 |
11 |
|
T4 |
6 |
lower_val |
lower_val |
auto[0] |
50893 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T15 |
43 |
lower_val |
lower_val |
auto[1] |
34123 |
1 |
|
|
T2 |
53 |
|
T3 |
7 |
|
T4 |
2 |
zero_val |
higher_val |
auto[0] |
706 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T5 |
1 |
zero_val |
higher_val |
auto[1] |
198 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T22 |
2 |
zero_val |
lower_val |
auto[0] |
687 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
193 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T22 |
2 |