Group : kmac_env_pkg::kmac_env_cov::error_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::kmac_env_cov::error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
89.66 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 21 3 18 85.71
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cmd 4 0 4 100.00 100 1 1 0
kmac_err_code 9 3 6 66.67 100 1 1 0
mode 3 0 3 100.00 100 1 1 0
strength 5 0 5 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_invalid_cmd_in_app_active 1 0 1 100.00 100 1 1 0
all_invalid_mode_strength_cfgs 7 0 7 100.00 100 1 1 0


Summary for Variable cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[CmdNone] 0 Excluded
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CmdStart] 650 1 T29 21 T49 9 T50 1
auto[CmdProcess] 90 1 T29 1 T50 1 T85 1
auto[CmdManualRun] 318 1 T29 7 T50 5 T85 4
auto[CmdDone] 1281 1 T29 42 T49 17 T50 5



Summary for Variable kmac_err_code

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 9 3 6 66.67


Automatically Generated Bins for kmac_err_code

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[ErrFatalError] 0 1 1
auto[ErrPackerIntegrity] 0 1 1
auto[ErrMsgFifoIntegrity] 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
auto[ErrNone] 0 Excluded
auto[ErrWaitTimerExpired] 0 Illegal
auto[ErrIncorrectEntropyMode] 0 Illegal
auto[ErrSwHashingWithoutEntropyReady] 0 Illegal
auto[ErrShadowRegUpdate] 0 Illegal
il 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ErrKeyNotValid] 50 1 T18 1 T20 1 T21 1
auto[ErrSwPushedMsgFifo] 60 1 T29 1 T30 1 T145 2
auto[ErrSwIssuedCmdInAppActive] 35 1 T29 1 T30 1 T31 1
auto[ErrUnexpectedModeStrength] 551 1 T29 22 T49 6 T50 2
auto[ErrIncorrectFunctionName] 560 1 T29 15 T49 8 T30 12
auto[ErrSwCmdSequence] 1152 1 T29 32 T49 12 T50 10



Summary for Variable mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[Sha3] 353 1 T29 11 T50 5 T30 3
auto[Shake] 400 1 T29 8 T49 6 T85 1
auto[CShake] 1605 1 T29 52 T49 20 T50 7



Summary for Variable strength

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for strength

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[L128] 792 1 T29 17 T49 7 T50 4
auto[L224] 262 1 T29 15 T49 3 T30 2
auto[L256] 786 1 T18 1 T29 23 T20 1
auto[L384] 284 1 T29 9 T49 7 T85 1
auto[L512] 284 1 T29 7 T49 6 T30 4



Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
invalid_cmds 34 1 T29 1 T30 1 T146 1



Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 7 0 7 100.00


User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sha3_128_cfgs 153 1 T29 5 T50 2 T30 1
shake_224_invalid_cfg 33 1 T29 3 T30 1 T32 1
shake_384_invalid_cfg 33 1 T49 1 T85 1 T30 1
shake_512_invalid_cfg 29 1 T29 1 T49 1 T30 1
cshake_224_invalid_cfg 83 1 T29 4 T49 1 T30 1
cshake_384_invalid_cfg 112 1 T29 5 T49 2 T145 1
cshake_512_invalid_cfg 108 1 T29 4 T49 1 T30 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%