Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 3 0 3 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 100697914 1 T1 1 T2 112563 T3 346
all_pins[1] 100697914 1 T1 1 T2 112563 T3 346
all_pins[2] 100697914 1 T1 1 T2 112563 T3 346



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 301338619 1 T1 3 T2 337316 T3 994
values[0x1] 755123 1 T2 373 T3 44 T4 9
transitions[0x0=>0x1] 753693 1 T2 373 T3 44 T4 9
transitions[0x1=>0x0] 753717 1 T2 373 T3 44 T4 9



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 0 12 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 100189553 1 T1 1 T2 112190 T3 302
all_pins[0] values[0x1] 508361 1 T2 373 T3 44 T4 9
all_pins[0] transitions[0x0=>0x1] 508350 1 T2 373 T3 44 T4 9
all_pins[0] transitions[0x1=>0x0] 62 1 T44 8 T153 4 T154 3
all_pins[1] values[0x0] 100697841 1 T1 1 T2 112563 T3 346
all_pins[1] values[0x1] 73 1 T44 8 T153 4 T154 3
all_pins[1] transitions[0x0=>0x1] 62 1 T44 8 T153 4 T154 3
all_pins[1] transitions[0x1=>0x0] 246678 1 T22 72 T24 3528 T29 983
all_pins[2] values[0x0] 100451225 1 T1 1 T2 112563 T3 346
all_pins[2] values[0x1] 246689 1 T22 72 T24 3528 T29 983
all_pins[2] transitions[0x0=>0x1] 245281 1 T22 71 T24 3505 T29 983
all_pins[2] transitions[0x1=>0x0] 506977 1 T2 373 T3 44 T4 9

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