Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100040017	1			T1	110570		T2	5		T3	573094
all_values[1]	100040017	1			T1	110570		T2	5		T3	573094
all_values[2]	100040017	1			T1	110570		T2	5		T3	573094

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

534520

1

T1

14

T2

5

T3

24

auto[1]

299585531

1

T1

331696

T2

10

T3

171925

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298577814

1

T1

330594

T2

15

T3

170856

auto[1]

1542237

1

T1

1116

T3

10716

T4

366

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	193229	1			T1	5		T3	11		T14	6
all_values[0]	auto[0]	auto[1]	2238	1			T1	6		T3	10		T14	6
all_values[0]	auto[1]	auto[0]	99332709	1			T1	110193		T2	5		T3	569511
all_values[0]	auto[1]	auto[1]	511841	1			T1	366		T3	3562		T4	122
all_values[1]	auto[0]	auto[0]	185552	1			T2	5		T4	146		T15	178
all_values[1]	auto[0]	auto[1]	1585	1			T4	1		T15	2		T39	2
all_values[1]	auto[1]	auto[0]	99340386	1			T1	110198		T3	569522		T4	13375
all_values[1]	auto[1]	auto[1]	512494	1			T1	372		T3	3572		T4	121
all_values[2]	auto[0]	auto[0]	150355	1			T1	1		T3	1		T4	442
all_values[2]	auto[0]	auto[1]	1561	1			T1	2		T3	2		T4	2
all_values[2]	auto[1]	auto[0]	99375583	1			T1	110197		T2	5		T3	569521
all_values[2]	auto[1]	auto[1]	512518	1			T1	370		T3	3570		T4	120