Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326568 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
372918 |
1 |
|
|
T1 |
490 |
|
T3 |
4672 |
|
T4 |
162 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174753 |
1 |
|
|
T1 |
122 |
|
T3 |
1152 |
|
T4 |
49 |
lower_val |
173105 |
1 |
|
|
T1 |
123 |
|
T2 |
1 |
|
T3 |
1213 |
zero_val |
1878 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
7 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350396 |
1 |
|
|
T1 |
246 |
|
T3 |
2324 |
|
T4 |
76 |
lower_val |
349068 |
1 |
|
|
T1 |
246 |
|
T2 |
2 |
|
T3 |
2350 |
zero_val |
22 |
1 |
|
|
T161 |
2 |
|
T111 |
2 |
|
T162 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40826 |
1 |
|
|
T4 |
1 |
|
T15 |
44 |
|
T16 |
43 |
higher_val |
higher_val |
auto[1] |
46719 |
1 |
|
|
T1 |
60 |
|
T3 |
574 |
|
T4 |
29 |
higher_val |
lower_val |
auto[0] |
41131 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
50 |
higher_val |
lower_val |
auto[1] |
46071 |
1 |
|
|
T1 |
61 |
|
T3 |
577 |
|
T4 |
19 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T162 |
1 |
|
T163 |
1 |
|
T164 |
1 |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T111 |
1 |
|
T165 |
1 |
|
T166 |
1 |
lower_val |
higher_val |
auto[0] |
40206 |
1 |
|
|
T15 |
49 |
|
T16 |
45 |
|
T18 |
39 |
lower_val |
higher_val |
auto[1] |
46617 |
1 |
|
|
T1 |
59 |
|
T3 |
605 |
|
T4 |
14 |
lower_val |
lower_val |
auto[0] |
40138 |
1 |
|
|
T2 |
1 |
|
T15 |
44 |
|
T16 |
45 |
lower_val |
lower_val |
auto[1] |
46137 |
1 |
|
|
T1 |
64 |
|
T3 |
608 |
|
T4 |
12 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T162 |
1 |
|
T167 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
5 |
1 |
|
|
T161 |
1 |
|
T168 |
1 |
|
T165 |
3 |
zero_val |
higher_val |
auto[0] |
660 |
1 |
|
|
T4 |
1 |
|
T15 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
258 |
1 |
|
|
T3 |
3 |
|
T23 |
3 |
|
T169 |
4 |
zero_val |
lower_val |
auto[0] |
689 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
271 |
1 |
|
|
T3 |
3 |
|
T169 |
4 |
|
T170 |
4 |