Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
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Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
hash_mode 3 0 3 100.00 100 1 1 0
kmac_mode 2 0 2 100.00 100 1 1 2
msgfifo_depth 11 0 11 100.00 100 1 1 0
msgfifo_empty 2 0 2 100.00 100 1 1 2
msgfifo_full 2 0 2 100.00 100 1 1 2


Summary for Variable hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 11369885 1 T4 13671 T15 10471 T16 11462
shake 55229484 1 T2 4 T3 568419 T4 2932
sha3 35381464 1 T1 110077 T4 837 T14 112691



Summary for Variable kmac_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 90609861 1 T1 110077 T2 4 T3 568419
auto[1] 11370972 1 T4 13671 T15 10477 T16 11476



Summary for Variable msgfifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for msgfifo_depth

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
depth[0x00] 100442779 1 T1 106092 T2 4 T3 560496
depth[0x01] 884548 1 T1 3985 T3 7923 T4 393
depth[0x02] 211631 1 T4 156 T18 360 T19 9
depth[0x03] 172631 1 T4 132 T18 327 T19 10
depth[0x04] 109579 1 T4 66 T18 149 T19 4
depth[0x05] 65854 1 T4 18 T18 33 T19 4
depth[0x06] 26452 1 T41 321 T24 117 T42 1055
depth[0x07] 561 1 T41 16 T52 7 T144 3
depth[0x08] 2154 1 T41 25 T24 12 T42 87
depth[0x09] 1908 1 T41 38 T24 6 T42 41
depth[0x0a] 62736 1 T41 926 T24 286 T42 2033



Summary for Variable msgfifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for msgfifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1538054 1 T1 3985 T3 7923 T4 765
auto[1] 100442779 1 T1 106092 T2 4 T3 560496



Summary for Variable msgfifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for msgfifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 101918097 1 T1 110077 T2 4 T3 568419
auto[1] 62736 1 T41 926 T24 286 T42 2033

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%