Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100040017	1			T1	110570		T2	5		T3	573094
all_pins[1]	100040017	1			T1	110570		T2	5		T3	573094
all_pins[2]	100040017	1			T1	110570		T2	5		T3	573094

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299268202	1			T1	331344		T2	15		T3	171572
values[0x1]	851849	1			T1	366		T3	3562		T4	122
transitions[0x0=>0x1]	849780	1			T1	366		T3	3562		T4	122
transitions[0x1=>0x0]	849800	1			T1	366		T3	3562		T4	122

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99528176	1			T1	110204		T2	5		T3	569532
all_pins[0]	values[0x1]	511841	1			T1	366		T3	3562		T4	122
all_pins[0]	transitions[0x0=>0x1]	511831	1			T1	366		T3	3562		T4	122
all_pins[0]	transitions[0x1=>0x0]	83	1			T31	3		T33	3		T182	3
all_pins[1]	values[0x0]	100039924	1			T1	110570		T2	5		T3	573094
all_pins[1]	values[0x1]	93	1			T31	3		T33	3		T182	3
all_pins[1]	transitions[0x0=>0x1]	78	1			T31	3		T33	3		T182	3
all_pins[1]	transitions[0x1=>0x0]	339900	1			T22	12792		T23	2458		T27	852
all_pins[2]	values[0x0]	99700102	1			T1	110570		T2	5		T3	573094
all_pins[2]	values[0x1]	339915	1			T22	12792		T23	2458		T27	852
all_pins[2]	transitions[0x0=>0x1]	337871	1			T22	12710		T23	2437		T27	852
all_pins[2]	transitions[0x1=>0x0]	509817	1			T1	366		T3	3562		T4	122