Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T118 4 T171 4 T172 7
all_values[1] 278 1 T118 4 T171 4 T172 7
all_values[2] 278 1 T118 4 T171 4 T172 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 427 1 T118 2 T171 5 T172 8
auto[1] 407 1 T118 10 T171 7 T172 13


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 421 1 T118 8 T171 8 T172 13
auto[1] 413 1 T118 4 T171 4 T172 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 523 1 T118 9 T171 8 T172 13
auto[1] 311 1 T118 3 T171 4 T172 8


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 67 1 T118 2 T171 2 T172 3
all_values[0] auto[0] auto[0] auto[1] 25 1 T173 2 T154 1 T174 3
all_values[0] auto[0] auto[1] auto[0] 65 1 T118 2 T171 1 T172 1
all_values[0] auto[0] auto[1] auto[1] 27 1 T175 2 T176 1 T177 1
all_values[0] auto[1] auto[0] auto[1] 50 1 T171 1 T178 2 T173 1
all_values[0] auto[1] auto[1] auto[1] 44 1 T172 3 T178 1 T179 1
all_values[1] auto[0] auto[0] auto[0] 87 1 T172 1 T178 3 T173 2
all_values[1] auto[0] auto[1] auto[0] 85 1 T118 3 T171 2 T172 4
all_values[1] auto[1] auto[0] auto[1] 56 1 T172 1 T178 2 T173 5
all_values[1] auto[1] auto[1] auto[1] 50 1 T118 1 T171 2 T172 1
all_values[2] auto[0] auto[0] auto[0] 67 1 T171 2 T172 3 T178 2
all_values[2] auto[0] auto[0] auto[1] 16 1 T153 3 T180 1 T181 1
all_values[2] auto[0] auto[1] auto[0] 50 1 T118 1 T171 1 T172 1
all_values[2] auto[0] auto[1] auto[1] 34 1 T118 1 T173 1 T154 1
all_values[2] auto[1] auto[0] auto[1] 59 1 T178 1 T173 1 T153 1
all_values[2] auto[1] auto[1] auto[1] 52 1 T118 2 T171 1 T172 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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