Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102912406	1			T1	22622		T13	556677		T15	285
all_values[1]	102912406	1			T1	22622		T13	556677		T15	285
all_values[2]	102912406	1			T1	22622		T13	556677		T15	285

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

574024

1

T13

12

T15

76

T16

8350

auto[1]

308163194

1

T1

67866

T13

167001

T15

779

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307189065

1

T1

67188

T13

165950

T15

816

auto[1]

1548153

1

T1

678

T13

10530

T15

39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162677	1			T13	6		T15	5		T16	4946
all_values[0]	auto[0]	auto[1]	2148	1			T13	6		T15	2		T16	8
all_values[0]	auto[1]	auto[0]	102233678	1			T1	22396		T13	553161		T15	267
all_values[0]	auto[1]	auto[1]	513903	1			T1	226		T13	3504		T15	11
all_values[1]	auto[0]	auto[0]	220289	1			T15	65		T16	1696		T17	48
all_values[1]	auto[0]	auto[1]	1593	1			T15	4		T16	2		T17	13
all_values[1]	auto[1]	auto[0]	102176066	1			T1	22396		T13	553167		T15	207
all_values[1]	auto[1]	auto[1]	514458	1			T1	226		T13	3510		T15	9
all_values[2]	auto[0]	auto[0]	185679	1			T16	1696		T17	141		T19	645
all_values[2]	auto[0]	auto[1]	1638	1			T16	2		T17	13		T19	6
all_values[2]	auto[1]	auto[0]	102210676	1			T1	22396		T13	553167		T15	272
all_values[2]	auto[1]	auto[1]	514413	1			T1	226		T13	3510		T15	13