Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
370204 |
1 |
|
|
T1 |
2 |
|
T13 |
2 |
|
T15 |
2 |
auto[1] |
332662 |
1 |
|
|
T1 |
396 |
|
T13 |
4672 |
|
T15 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176014 |
1 |
|
|
T1 |
96 |
|
T13 |
1186 |
|
T15 |
6 |
lower_val |
174435 |
1 |
|
|
T1 |
86 |
|
T13 |
1143 |
|
T15 |
3 |
zero_val |
1945 |
1 |
|
|
T1 |
3 |
|
T13 |
9 |
|
T15 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
351824 |
1 |
|
|
T1 |
214 |
|
T13 |
2302 |
|
T15 |
10 |
lower_val |
351028 |
1 |
|
|
T1 |
184 |
|
T13 |
2372 |
|
T15 |
8 |
zero_val |
14 |
1 |
|
|
T80 |
2 |
|
T150 |
2 |
|
T151 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46080 |
1 |
|
|
T13 |
1 |
|
T17 |
17 |
|
T18 |
60 |
higher_val |
higher_val |
auto[1] |
41797 |
1 |
|
|
T1 |
49 |
|
T13 |
542 |
|
T15 |
4 |
higher_val |
lower_val |
auto[0] |
46522 |
1 |
|
|
T17 |
12 |
|
T18 |
68 |
|
T19 |
9 |
higher_val |
lower_val |
auto[1] |
41613 |
1 |
|
|
T1 |
47 |
|
T13 |
643 |
|
T15 |
2 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T150 |
1 |
|
T71 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
45996 |
1 |
|
|
T17 |
9 |
|
T18 |
49 |
|
T19 |
16 |
lower_val |
higher_val |
auto[1] |
41284 |
1 |
|
|
T1 |
48 |
|
T13 |
572 |
|
T15 |
1 |
lower_val |
lower_val |
auto[0] |
45822 |
1 |
|
|
T1 |
1 |
|
T16 |
1 |
|
T17 |
8 |
lower_val |
lower_val |
auto[1] |
41330 |
1 |
|
|
T1 |
37 |
|
T13 |
571 |
|
T15 |
2 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T151 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T80 |
1 |
|
T71 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
719 |
1 |
|
|
T13 |
1 |
|
T17 |
1 |
|
T19 |
1 |
zero_val |
higher_val |
auto[1] |
242 |
1 |
|
|
T1 |
2 |
|
T13 |
3 |
|
T17 |
1 |
zero_val |
lower_val |
auto[0] |
702 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
282 |
1 |
|
|
T13 |
5 |
|
T17 |
1 |
|
T84 |
1 |