Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102912406	1			T1	22622		T13	556677		T15	285
all_pins[1]	102912406	1			T1	22622		T13	556677		T15	285
all_pins[2]	102912406	1			T1	22622		T13	556677		T15	285

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	307902495	1			T1	67640		T13	166652		T15	844
values[0x1]	834723	1			T1	226		T13	3504		T15	11
transitions[0x0=>0x1]	832781	1			T1	226		T13	3504		T15	11
transitions[0x1=>0x0]	832801	1			T1	226		T13	3504		T15	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	102398503	1			T1	22396		T13	553173		T15	274
all_pins[0]	values[0x1]	513903	1			T1	226		T13	3504		T15	11
all_pins[0]	transitions[0x0=>0x1]	513894	1			T1	226		T13	3504		T15	11
all_pins[0]	transitions[0x1=>0x0]	86	1			T39	3		T162	5		T163	10
all_pins[1]	values[0x0]	102912311	1			T1	22622		T13	556677		T15	285
all_pins[1]	values[0x1]	95	1			T39	3		T162	5		T163	10
all_pins[1]	transitions[0x0=>0x1]	85	1			T39	3		T162	5		T163	10
all_pins[1]	transitions[0x1=>0x0]	320715	1			T25	530		T26	1206		T21	14657
all_pins[2]	values[0x0]	102591681	1			T1	22622		T13	556677		T15	285
all_pins[2]	values[0x1]	320725	1			T25	530		T26	1206		T21	14657
all_pins[2]	transitions[0x0=>0x1]	318802	1			T25	530		T26	1206		T21	14556
all_pins[2]	transitions[0x1=>0x0]	512000	1			T1	226		T13	3504		T15	11