Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100278086	1			T2	308		T3	937		T12	294
all_values[1]	100278086	1			T2	308		T3	937		T12	294
all_values[2]	100278086	1			T2	308		T3	937		T12	294

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570038

1

T2

18

T3

85

T12

67

auto[1]

300264220

1

T2

906

T3

2726

T12

815

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299294799

1

T2

888

T3

2583

T12

846

auto[1]

1539459

1

T2

36

T3

228

T12

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	178139	1			T2	4		T13	4292		T15	2
all_values[0]	auto[0]	auto[1]	2227	1			T2	2		T13	6		T17	2
all_values[0]	auto[1]	auto[0]	99586794	1			T2	292		T3	861		T12	282
all_values[0]	auto[1]	auto[1]	510926	1			T2	10		T3	76		T12	12
all_values[1]	auto[0]	auto[0]	207895	1			T2	4		T3	58		T13	195
all_values[1]	auto[0]	auto[1]	1712	1			T2	2		T3	3		T13	2
all_values[1]	auto[1]	auto[0]	99557038	1			T2	292		T3	803		T12	282
all_values[1]	auto[1]	auto[1]	511441	1			T2	10		T3	73		T12	12
all_values[2]	auto[0]	auto[0]	178449	1			T2	4		T3	23		T12	63
all_values[2]	auto[0]	auto[1]	1616	1			T2	2		T3	1		T12	4
all_values[2]	auto[1]	auto[0]	99586484	1			T2	292		T3	838		T12	219
all_values[2]	auto[1]	auto[1]	511537	1			T2	10		T3	75		T12	8