Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
378732 |
1 |
|
|
T2 |
18 |
|
T3 |
106 |
|
T12 |
18 |
auto[1] |
318330 |
1 |
|
|
T13 |
208 |
|
T15 |
14 |
|
T18 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173506 |
1 |
|
|
T2 |
4 |
|
T3 |
23 |
|
T12 |
2 |
lower_val |
173391 |
1 |
|
|
T2 |
4 |
|
T3 |
28 |
|
T12 |
5 |
zero_val |
1842 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T12 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347940 |
1 |
|
|
T2 |
10 |
|
T3 |
54 |
|
T12 |
6 |
lower_val |
349110 |
1 |
|
|
T2 |
8 |
|
T3 |
52 |
|
T12 |
12 |
zero_val |
12 |
1 |
|
|
T146 |
2 |
|
T147 |
2 |
|
T148 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47046 |
1 |
|
|
T2 |
2 |
|
T3 |
12 |
|
T12 |
1 |
higher_val |
higher_val |
auto[1] |
39938 |
1 |
|
|
T13 |
23 |
|
T15 |
3 |
|
T18 |
106 |
higher_val |
lower_val |
auto[0] |
46907 |
1 |
|
|
T2 |
2 |
|
T3 |
11 |
|
T12 |
1 |
higher_val |
lower_val |
auto[1] |
39612 |
1 |
|
|
T13 |
18 |
|
T15 |
1 |
|
T18 |
82 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T147 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T146 |
1 |
|
T148 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
47039 |
1 |
|
|
T2 |
4 |
|
T3 |
14 |
|
T14 |
3 |
lower_val |
higher_val |
auto[1] |
39466 |
1 |
|
|
T13 |
29 |
|
T15 |
2 |
|
T18 |
105 |
lower_val |
lower_val |
auto[0] |
47184 |
1 |
|
|
T3 |
14 |
|
T12 |
5 |
|
T17 |
65 |
lower_val |
lower_val |
auto[1] |
39699 |
1 |
|
|
T13 |
25 |
|
T18 |
93 |
|
T41 |
39 |
lower_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T146 |
1 |
|
T149 |
2 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
676 |
1 |
|
|
T2 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
228 |
1 |
|
|
T23 |
2 |
|
T84 |
1 |
|
T46 |
3 |
zero_val |
lower_val |
auto[0] |
706 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T17 |
1 |
zero_val |
lower_val |
auto[1] |
232 |
1 |
|
|
T26 |
1 |
|
T23 |
2 |
|
T84 |
1 |