Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100278086	1			T2	308		T3	937		T12	294
all_pins[1]	100278086	1			T2	308		T3	937		T12	294
all_pins[2]	100278086	1			T2	308		T3	937		T12	294

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300053470	1			T2	914		T3	2735		T12	870
values[0x1]	780788	1			T2	10		T3	76		T12	12
transitions[0x0=>0x1]	779132	1			T2	10		T3	76		T12	12
transitions[0x1=>0x0]	779153	1			T2	10		T3	76		T12	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99767160	1			T2	298		T3	861		T12	282
all_pins[0]	values[0x1]	510926	1			T2	10		T3	76		T12	12
all_pins[0]	transitions[0x0=>0x1]	510918	1			T2	10		T3	76		T12	12
all_pins[0]	transitions[0x1=>0x0]	60	1			T160	2		T161	3		T162	2
all_pins[1]	values[0x0]	100278018	1			T2	308		T3	937		T12	294
all_pins[1]	values[0x1]	68	1			T160	2		T161	3		T162	2
all_pins[1]	transitions[0x0=>0x1]	57	1			T160	2		T161	3		T162	2
all_pins[1]	transitions[0x1=>0x0]	269783	1			T23	4521		T30	1352		T24	1456
all_pins[2]	values[0x0]	100008292	1			T2	308		T3	937		T12	294
all_pins[2]	values[0x1]	269794	1			T23	4521		T30	1352		T24	1456
all_pins[2]	transitions[0x0=>0x1]	268157	1			T23	4496		T30	1352		T24	1443
all_pins[2]	transitions[0x1=>0x0]	509310	1			T2	10		T3	76		T12	12