Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	679	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5580	1			T3	10		T13	18		T29	26
len_601_800	12708	1			T3	20		T13	40		T29	68
len_401_600	8491	1			T3	8		T13	28		T15	2
len_201_400	16556	1			T3	8		T13	9		T29	24
len_65_200	74462	1			T3	3		T13	6		T15	1
len_min_for_xof_require_squeeze	997	1			T22	1		T42	9		T105	9
len_keccak_block_sizes[72]	772	1			T41	1		T42	9		T26	1
len_keccak_block_sizes[104]	770	1			T42	9		T105	9		T180	5
len_keccak_block_sizes[136]	760	1			T41	1		T42	9		T26	1
len_keccak_block_sizes[144]	285	1			T180	5		T181	5		T182	1
len_keccak_block_sizes[168]	296	1			T180	5		T181	5		T47	1
len_datapath_width	14121	1			T2	3		T3	1		T12	3
len_2_63	214752	1			T2	6		T3	3		T12	6
len_1	55	1			T76	1		T102	1		T48	1