Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
78.57 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 3 5 62.50


Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
share 2 0 2 100.00 100 1 1 2
state_read_mask 4 0 4 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
state_mask_share_cross 8 3 5 62.50 100 1 1 0


Summary for Variable share

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for share

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10859132 1 T2 96 T3 8658 T12 96
auto[1] 25924001 1 T2 450 T3 12590 T12 450



Summary for Variable state_read_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for state_read_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 36662778 1 T2 546 T3 21210 T12 546
triple_byte_access 39983 1 T3 11 T13 20 T29 51
halfword_access 40506 1 T3 11 T13 30 T15 3
byte_access 39866 1 T3 16 T13 28 T15 1



Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 3 5 62.50 3


Automatically Generated Cross Bins for state_mask_share_cross

Uncovered bins
sharestate_read_maskCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [triple_byte_access , halfword_access , byte_access] -- -- 3


Covered bins
sharestate_read_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 10738777 1 T2 96 T3 8620 T12 96
auto[0] triple_byte_access 39983 1 T3 11 T13 20 T29 51
auto[0] halfword_access 40506 1 T3 11 T13 30 T15 3
auto[0] byte_access 39866 1 T3 16 T13 28 T15 1
auto[1] word_access 25924001 1 T2 450 T3 12590 T12 450

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%