Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99799316	1			T1	1639		T3	9047		T9	454868
all_values[1]	99799316	1			T1	1639		T3	9047		T9	454868
all_values[2]	99799316	1			T1	1639		T3	9047		T9	454868

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577560

1

T1

15

T9

21

T13

713

auto[1]

298820388

1

T1

4902

T3

27141

T9

136458

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297870462

1

T1

4293

T3

26874

T9

135437

auto[1]

1527486

1

T1

624

T3

267

T9

10227

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	178025	1			T1	2		T9	1		T15	1
all_values[0]	auto[0]	auto[1]	2099	1			T1	2		T9	2		T15	2
all_values[0]	auto[1]	auto[0]	99112129	1			T1	1429		T3	8958		T9	451458
all_values[0]	auto[1]	auto[1]	507063	1			T1	206		T3	89		T9	3407
all_values[1]	auto[0]	auto[0]	201455	1			T9	1		T15	1		T16	1
all_values[1]	auto[0]	auto[1]	1489	1			T9	2		T15	2		T16	2
all_values[1]	auto[1]	auto[0]	99088699	1			T1	1431		T3	8958		T9	451458
all_values[1]	auto[1]	auto[1]	507673	1			T1	208		T3	89		T9	3407
all_values[2]	auto[0]	auto[0]	192843	1			T1	8		T9	10		T13	706
all_values[2]	auto[0]	auto[1]	1649	1			T1	3		T9	5		T13	7
all_values[2]	auto[1]	auto[0]	99097311	1			T1	1423		T3	8958		T9	451449
all_values[2]	auto[1]	auto[1]	507513	1			T1	205		T3	89		T9	3404