Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
365526 |
1 |
|
|
T1 |
286 |
|
T2 |
2 |
|
T3 |
128 |
auto[1] |
327072 |
1 |
|
|
T9 |
4528 |
|
T13 |
340 |
|
T16 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173704 |
1 |
|
|
T1 |
70 |
|
T3 |
42 |
|
T9 |
1124 |
lower_val |
170767 |
1 |
|
|
T1 |
82 |
|
T3 |
34 |
|
T9 |
1080 |
zero_val |
1795 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346712 |
1 |
|
|
T1 |
164 |
|
T2 |
2 |
|
T3 |
72 |
lower_val |
345876 |
1 |
|
|
T1 |
122 |
|
T3 |
56 |
|
T9 |
2286 |
zero_val |
10 |
1 |
|
|
T118 |
2 |
|
T160 |
2 |
|
T161 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46091 |
1 |
|
|
T1 |
42 |
|
T3 |
24 |
|
T15 |
507 |
higher_val |
higher_val |
auto[1] |
41152 |
1 |
|
|
T9 |
563 |
|
T13 |
44 |
|
T16 |
108 |
higher_val |
lower_val |
auto[0] |
45615 |
1 |
|
|
T1 |
28 |
|
T3 |
18 |
|
T13 |
1 |
higher_val |
lower_val |
auto[1] |
40842 |
1 |
|
|
T9 |
561 |
|
T13 |
43 |
|
T16 |
106 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T161 |
1 |
|
T162 |
1 |
|
T163 |
1 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T118 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
45067 |
1 |
|
|
T1 |
47 |
|
T3 |
20 |
|
T15 |
585 |
lower_val |
higher_val |
auto[1] |
40424 |
1 |
|
|
T9 |
537 |
|
T13 |
40 |
|
T16 |
90 |
lower_val |
lower_val |
auto[0] |
44830 |
1 |
|
|
T1 |
35 |
|
T3 |
14 |
|
T15 |
579 |
lower_val |
lower_val |
auto[1] |
40445 |
1 |
|
|
T9 |
543 |
|
T13 |
50 |
|
T16 |
88 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T160 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
649 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
251 |
1 |
|
|
T9 |
3 |
|
T16 |
2 |
|
T118 |
2 |
zero_val |
lower_val |
auto[0] |
668 |
1 |
|
|
T9 |
1 |
|
T13 |
1 |
|
T15 |
2 |
zero_val |
lower_val |
auto[1] |
227 |
1 |
|
|
T9 |
5 |
|
T118 |
6 |
|
T25 |
2 |