Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99799316	1			T1	1639		T3	9047		T9	454868
all_pins[1]	99799316	1			T1	1639		T3	9047		T9	454868
all_pins[2]	99799316	1			T1	1639		T3	9047		T9	454868

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298594440	1			T1	4711		T3	27052		T9	136119
values[0x1]	803508	1			T1	206		T3	89		T9	3407
transitions[0x0=>0x1]	801724	1			T1	206		T3	89		T9	3407
transitions[0x1=>0x0]	801749	1			T1	206		T3	89		T9	3407

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99292253	1			T1	1433		T3	8958		T9	451461
all_pins[0]	values[0x1]	507063	1			T1	206		T3	89		T9	3407
all_pins[0]	transitions[0x0=>0x1]	507054	1			T1	206		T3	89		T9	3407
all_pins[0]	transitions[0x1=>0x0]	66	1			T176	4		T54	10		T177	4
all_pins[1]	values[0x0]	99799241	1			T1	1639		T3	9047		T9	454868
all_pins[1]	values[0x1]	75	1			T176	4		T54	10		T177	4
all_pins[1]	transitions[0x0=>0x1]	64	1			T176	4		T54	10		T177	4
all_pins[1]	transitions[0x1=>0x0]	296359	1			T23	5688		T24	5552		T30	10
all_pins[2]	values[0x0]	99502946	1			T1	1639		T3	9047		T9	454868
all_pins[2]	values[0x1]	296370	1			T23	5688		T24	5552		T30	10
all_pins[2]	transitions[0x0=>0x1]	294606	1			T23	5652		T24	5519		T30	9
all_pins[2]	transitions[0x1=>0x0]	505324	1			T1	206		T3	89		T9	3407