Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	619	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5386	1			T3	7		T13	23		T17	22
len_601_800	12274	1			T3	25		T13	53		T17	76
len_401_600	8020	1			T3	11		T13	43		T17	43
len_201_400	16332	1			T3	10		T9	251		T13	26
len_65_200	73771	1			T1	71		T3	6		T9	680
len_min_for_xof_require_squeeze	999	1			T9	10		T15	10		T117	1
len_keccak_block_sizes[72]	755	1			T9	5		T15	5		T18	1
len_keccak_block_sizes[104]	744	1			T1	1		T9	5		T15	5
len_keccak_block_sizes[136]	748	1			T1	1		T9	5		T15	5
len_keccak_block_sizes[144]	298	1			T9	5		T15	5		T115	1
len_keccak_block_sizes[168]	284	1			T9	5		T15	5		T29	1
len_datapath_width	14107	1			T1	3		T9	5		T15	5
len_2_63	214631	1			T1	67		T3	3		T9	1329
len_1	44	1			T1	2		T25	1		T90	1