Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10575091 |
1 |
|
|
T1 |
5118 |
|
T3 |
10080 |
|
T9 |
47900 |
auto[1] |
25495418 |
1 |
|
|
T1 |
9736 |
|
T3 |
14666 |
|
T9 |
141800 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
35952094 |
1 |
|
|
T1 |
14761 |
|
T3 |
24698 |
|
T9 |
188764 |
triple_byte_access |
39306 |
1 |
|
|
T1 |
38 |
|
T3 |
21 |
|
T9 |
310 |
halfword_access |
39941 |
1 |
|
|
T1 |
34 |
|
T3 |
11 |
|
T9 |
316 |
byte_access |
39168 |
1 |
|
|
T1 |
21 |
|
T3 |
16 |
|
T9 |
310 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10456676 |
1 |
|
|
T1 |
5025 |
|
T3 |
10032 |
|
T9 |
46964 |
auto[0] |
triple_byte_access |
39306 |
1 |
|
|
T1 |
38 |
|
T3 |
21 |
|
T9 |
310 |
auto[0] |
halfword_access |
39941 |
1 |
|
|
T1 |
34 |
|
T3 |
11 |
|
T9 |
316 |
auto[0] |
byte_access |
39168 |
1 |
|
|
T1 |
21 |
|
T3 |
16 |
|
T9 |
310 |
auto[1] |
word_access |
25495418 |
1 |
|
|
T1 |
9736 |
|
T3 |
14666 |
|
T9 |
141800 |