Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100647516	1			T1	213930		T2	284		T3	569063
all_values[1]	100647516	1			T1	213930		T2	284		T3	569063
all_values[2]	100647516	1			T1	213930		T2	284		T3	569063

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

433530

1

T2

77

T3

6

T13

7

auto[1]

301509018

1

T1

641790

T2

775

T3

170718

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300405861

1

T1

640116

T2

816

T3

169672

auto[1]

1536687

1

T1

1674

T2

36

T3

10467

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142140	1			T3	1		T14	4		T16	28
all_values[0]	auto[0]	auto[1]	2049	1			T3	2		T14	2		T16	4
all_values[0]	auto[1]	auto[0]	99993147	1			T1	213372		T2	272		T3	565573
all_values[0]	auto[1]	auto[1]	510180	1			T1	558		T2	12		T3	3487
all_values[1]	auto[0]	auto[0]	152598	1			T2	7		T15	11		T16	28
all_values[1]	auto[0]	auto[1]	1571	1			T2	1		T15	5		T16	4
all_values[1]	auto[1]	auto[0]	99982689	1			T1	213372		T2	265		T3	565574
all_values[1]	auto[1]	auto[1]	510658	1			T1	558		T2	11		T3	3489
all_values[2]	auto[0]	auto[0]	133639	1			T2	65		T3	1		T13	5
all_values[2]	auto[0]	auto[1]	1533	1			T2	4		T3	2		T13	2
all_values[2]	auto[1]	auto[0]	100001648	1			T1	213372		T2	207		T3	565573
all_values[2]	auto[1]	auto[1]	510696	1			T1	558		T2	8		T3	3487