Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
392668 |
1 |
|
|
T1 |
748 |
|
T2 |
18 |
|
T3 |
4674 |
auto[1] |
303612 |
1 |
|
|
T13 |
778 |
|
T15 |
490 |
|
T18 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174960 |
1 |
|
|
T1 |
174 |
|
T2 |
6 |
|
T3 |
1242 |
lower_val |
172449 |
1 |
|
|
T1 |
168 |
|
T2 |
1 |
|
T3 |
1132 |
zero_val |
1815 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348862 |
1 |
|
|
T1 |
372 |
|
T2 |
10 |
|
T3 |
2290 |
lower_val |
347412 |
1 |
|
|
T1 |
376 |
|
T2 |
8 |
|
T3 |
2384 |
zero_val |
6 |
1 |
|
|
T68 |
2 |
|
T162 |
2 |
|
T163 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
49406 |
1 |
|
|
T1 |
91 |
|
T2 |
3 |
|
T3 |
601 |
higher_val |
higher_val |
auto[1] |
38236 |
1 |
|
|
T13 |
94 |
|
T15 |
55 |
|
T18 |
1 |
higher_val |
lower_val |
auto[0] |
48974 |
1 |
|
|
T1 |
83 |
|
T2 |
3 |
|
T3 |
641 |
higher_val |
lower_val |
auto[1] |
38341 |
1 |
|
|
T13 |
92 |
|
T15 |
55 |
|
T18 |
3 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T68 |
1 |
|
T163 |
2 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
48763 |
1 |
|
|
T1 |
96 |
|
T2 |
1 |
|
T3 |
554 |
lower_val |
higher_val |
auto[1] |
37715 |
1 |
|
|
T13 |
100 |
|
T15 |
69 |
|
T18 |
2 |
lower_val |
lower_val |
auto[0] |
48398 |
1 |
|
|
T1 |
72 |
|
T3 |
578 |
|
T12 |
15 |
lower_val |
lower_val |
auto[1] |
37572 |
1 |
|
|
T13 |
95 |
|
T15 |
62 |
|
T18 |
3 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T68 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
697 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
zero_val |
higher_val |
auto[1] |
208 |
1 |
|
|
T13 |
1 |
|
T15 |
1 |
|
T164 |
2 |
zero_val |
lower_val |
auto[0] |
704 |
1 |
|
|
T3 |
3 |
|
T13 |
1 |
|
T15 |
1 |
zero_val |
lower_val |
auto[1] |
206 |
1 |
|
|
T13 |
1 |
|
T15 |
1 |
|
T164 |
4 |