Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100647516	1			T1	213930		T2	284		T3	569063
all_pins[1]	100647516	1			T1	213930		T2	284		T3	569063
all_pins[2]	100647516	1			T1	213930		T2	284		T3	569063

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301119469	1			T1	641232		T2	840		T3	170370
values[0x1]	823079	1			T1	558		T2	12		T3	3487
transitions[0x0=>0x1]	821156	1			T1	558		T2	12		T3	3487
transitions[0x1=>0x0]	821176	1			T1	558		T2	12		T3	3487

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100137336	1			T1	213372		T2	272		T3	565576
all_pins[0]	values[0x1]	510180	1			T1	558		T2	12		T3	3487
all_pins[0]	transitions[0x0=>0x1]	510170	1			T1	558		T2	12		T3	3487
all_pins[0]	transitions[0x1=>0x0]	60	1			T44	3		T175	3		T176	3
all_pins[1]	values[0x0]	100647446	1			T1	213930		T2	284		T3	569063
all_pins[1]	values[0x1]	70	1			T44	3		T175	3		T176	3
all_pins[1]	transitions[0x0=>0x1]	60	1			T44	3		T175	3		T176	3
all_pins[1]	transitions[0x1=>0x0]	312819	1			T12	336		T23	13971		T24	1744
all_pins[2]	values[0x0]	100334687	1			T1	213930		T2	284		T3	569063
all_pins[2]	values[0x1]	312829	1			T12	336		T23	13971		T24	1744
all_pins[2]	transitions[0x0=>0x1]	310926	1			T12	336		T23	13880		T24	1726
all_pins[2]	transitions[0x1=>0x0]	508297	1			T1	558		T2	12		T3	3487