Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10778413 |
1 |
|
|
T1 |
2992 |
|
T2 |
96 |
|
T3 |
27235 |
| auto[1] |
25804256 |
1 |
|
|
T1 |
18700 |
|
T2 |
450 |
|
T3 |
116850 |
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| word_access |
36462786 |
1 |
|
|
T1 |
21692 |
|
T2 |
546 |
|
T3 |
143248 |
| triple_byte_access |
39891 |
1 |
|
|
T3 |
279 |
|
T12 |
14 |
|
T16 |
32 |
| halfword_access |
40188 |
1 |
|
|
T3 |
279 |
|
T12 |
11 |
|
T16 |
30 |
| byte_access |
39804 |
1 |
|
|
T3 |
279 |
|
T12 |
18 |
|
T16 |
37 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
word_access |
10658530 |
1 |
|
|
T1 |
2992 |
|
T2 |
96 |
|
T3 |
26398 |
| auto[0] |
triple_byte_access |
39891 |
1 |
|
|
T3 |
279 |
|
T12 |
14 |
|
T16 |
32 |
| auto[0] |
halfword_access |
40188 |
1 |
|
|
T3 |
279 |
|
T12 |
11 |
|
T16 |
30 |
| auto[0] |
byte_access |
39804 |
1 |
|
|
T3 |
279 |
|
T12 |
18 |
|
T16 |
37 |
| auto[1] |
word_access |
25804256 |
1 |
|
|
T1 |
18700 |
|
T2 |
450 |
|
T3 |
116850 |