Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100438033	1			T1	1		T2	1468		T3	25484
all_values[1]	100438033	1			T1	1		T2	1468		T3	25484
all_values[2]	100438033	1			T1	1		T2	1468		T3	25484

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

561066

1

T1

2

T2

22

T3

58

auto[1]

300753033

1

T1

1

T2

4382

T3

76394

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299785236

1

T1

3

T2

4020

T3

75765

auto[1]

1528863

1

T2

384

T3

687

T4

165

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	174780	1			T1	1		T14	1		T18	320
all_values[0]	auto[0]	auto[1]	1962	1			T14	2		T18	2		T189	2
all_values[0]	auto[1]	auto[0]	99753632	1			T2	1340		T3	25255		T4	5669
all_values[0]	auto[1]	auto[1]	507659	1			T2	128		T3	229		T4	55
all_values[1]	auto[0]	auto[0]	188558	1			T1	1		T2	19		T3	57
all_values[1]	auto[0]	auto[1]	1618	1			T2	3		T3	1		T13	2
all_values[1]	auto[1]	auto[0]	99739854	1			T2	1321		T3	25198		T4	5669
all_values[1]	auto[1]	auto[1]	508003	1			T2	125		T3	228		T4	55
all_values[2]	auto[0]	auto[0]	192539	1			T4	1		T14	4		T15	2
all_values[2]	auto[0]	auto[1]	1609	1			T14	3		T15	1		T68	1
all_values[2]	auto[1]	auto[0]	99735873	1			T1	1		T2	1340		T3	25255
all_values[2]	auto[1]	auto[1]	508012	1			T2	128		T3	229		T4	55