Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
386422 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
305966 |
1 |
|
|
T2 |
160 |
|
T3 |
346 |
|
T14 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173895 |
1 |
|
|
T2 |
48 |
|
T3 |
84 |
|
T4 |
34 |
lower_val |
170562 |
1 |
|
|
T1 |
1 |
|
T2 |
34 |
|
T3 |
77 |
zero_val |
1782 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347268 |
1 |
|
|
T1 |
2 |
|
T2 |
74 |
|
T3 |
174 |
lower_val |
345102 |
1 |
|
|
T2 |
88 |
|
T3 |
174 |
|
T4 |
56 |
zero_val |
18 |
1 |
|
|
T163 |
2 |
|
T164 |
2 |
|
T165 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
48280 |
1 |
|
|
T4 |
17 |
|
T13 |
1 |
|
T15 |
596 |
higher_val |
higher_val |
auto[1] |
38803 |
1 |
|
|
T2 |
21 |
|
T3 |
43 |
|
T14 |
96 |
higher_val |
lower_val |
auto[0] |
48320 |
1 |
|
|
T2 |
1 |
|
T4 |
17 |
|
T13 |
3 |
higher_val |
lower_val |
auto[1] |
38485 |
1 |
|
|
T2 |
26 |
|
T3 |
41 |
|
T14 |
89 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T166 |
1 |
|
T167 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
5 |
1 |
|
|
T165 |
1 |
|
T168 |
1 |
|
T169 |
1 |
lower_val |
higher_val |
auto[0] |
47681 |
1 |
|
|
T1 |
1 |
|
T4 |
11 |
|
T13 |
3 |
lower_val |
higher_val |
auto[1] |
37899 |
1 |
|
|
T2 |
13 |
|
T3 |
34 |
|
T14 |
99 |
lower_val |
lower_val |
auto[0] |
47446 |
1 |
|
|
T4 |
14 |
|
T13 |
1 |
|
T15 |
589 |
lower_val |
lower_val |
auto[1] |
37532 |
1 |
|
|
T2 |
21 |
|
T3 |
43 |
|
T14 |
101 |
lower_val |
zero_val |
auto[1] |
4 |
1 |
|
|
T163 |
2 |
|
T164 |
1 |
|
T165 |
1 |
zero_val |
higher_val |
auto[0] |
696 |
1 |
|
|
T1 |
1 |
|
T15 |
5 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
223 |
1 |
|
|
T170 |
5 |
|
T171 |
2 |
|
T172 |
1 |
zero_val |
lower_val |
auto[0] |
642 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
zero_val |
lower_val |
auto[1] |
221 |
1 |
|
|
T14 |
2 |
|
T110 |
2 |
|
T170 |
3 |