Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100438033	1			T1	1		T2	1468		T3	25484
all_pins[1]	100438033	1			T1	1		T2	1468		T3	25484
all_pins[2]	100438033	1			T1	1		T2	1468		T3	25484

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300501558	1			T1	3		T2	4276		T3	75098
values[0x1]	812541	1			T2	128		T3	1354		T4	55
transitions[0x0=>0x1]	810658	1			T2	128		T3	1354		T4	55
transitions[0x1=>0x0]	810681	1			T2	128		T3	1354		T4	55

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99930374	1			T1	1		T2	1340		T3	25255
all_pins[0]	values[0x1]	507659	1			T2	128		T3	229		T4	55
all_pins[0]	transitions[0x0=>0x1]	507643	1			T2	128		T3	229		T4	55
all_pins[0]	transitions[0x1=>0x0]	69	1			T190	3		T52	2		T191	5
all_pins[1]	values[0x0]	100437948	1			T1	1		T2	1468		T3	25484
all_pins[1]	values[0x1]	85	1			T190	3		T52	2		T191	5
all_pins[1]	transitions[0x0=>0x1]	68	1			T190	3		T52	2		T191	5
all_pins[1]	transitions[0x1=>0x0]	304780	1			T3	1125		T18	216		T48	478
all_pins[2]	values[0x0]	100133236	1			T1	1		T2	1468		T3	24359
all_pins[2]	values[0x1]	304797	1			T3	1125		T18	216		T48	478
all_pins[2]	transitions[0x0=>0x1]	302947	1			T3	1125		T18	216		T48	478
all_pins[2]	transitions[0x1=>0x0]	505832	1			T2	128		T3	229		T4	55