Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339647 |
1 |
|
|
T1 |
1 |
|
T2 |
81 |
|
T3 |
176 |
auto[1] |
3023 |
1 |
|
|
T3 |
1 |
|
T4 |
10 |
|
T16 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
306256 |
1 |
|
|
T1 |
1 |
|
T2 |
20 |
|
T3 |
42 |
auto[1] |
36414 |
1 |
|
|
T2 |
61 |
|
T3 |
135 |
|
T4 |
46 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329291 |
1 |
|
|
T1 |
1 |
|
T2 |
81 |
|
T3 |
149 |
auto[1] |
13379 |
1 |
|
|
T3 |
28 |
|
T4 |
20 |
|
T16 |
1 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13379 |
1 |
|
|
T3 |
28 |
|
T4 |
20 |
|
T16 |
1 |
sw_kmac_invalid_sideload |
329291 |
1 |
|
|
T1 |
1 |
|
T2 |
81 |
|
T3 |
149 |
app_valid_sideload |
13379 |
1 |
|
|
T3 |
28 |
|
T4 |
20 |
|
T16 |
1 |
app_invalid_sideload |
329291 |
1 |
|
|
T1 |
1 |
|
T2 |
81 |
|
T3 |
149 |