Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10656443 |
1 |
|
|
T2 |
13428 |
|
T3 |
26811 |
|
T4 |
7047 |
auto[1] |
25599703 |
1 |
|
|
T2 |
19416 |
|
T3 |
40338 |
|
T4 |
10778 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36137482 |
1 |
|
|
T2 |
32790 |
|
T3 |
67037 |
|
T4 |
17793 |
triple_byte_access |
39483 |
1 |
|
|
T2 |
15 |
|
T3 |
39 |
|
T4 |
7 |
halfword_access |
39703 |
1 |
|
|
T2 |
25 |
|
T3 |
26 |
|
T4 |
13 |
byte_access |
39478 |
1 |
|
|
T2 |
14 |
|
T3 |
47 |
|
T4 |
12 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10537779 |
1 |
|
|
T2 |
13374 |
|
T3 |
26699 |
|
T4 |
7015 |
auto[0] |
triple_byte_access |
39483 |
1 |
|
|
T2 |
15 |
|
T3 |
39 |
|
T4 |
7 |
auto[0] |
halfword_access |
39703 |
1 |
|
|
T2 |
25 |
|
T3 |
26 |
|
T4 |
13 |
auto[0] |
byte_access |
39478 |
1 |
|
|
T2 |
14 |
|
T3 |
47 |
|
T4 |
12 |
auto[1] |
word_access |
25599703 |
1 |
|
|
T2 |
19416 |
|
T3 |
40338 |
|
T4 |
10778 |