Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 284 1 T119 4 T182 7 T183 7
all_values[1] 284 1 T119 4 T182 7 T183 7
all_values[2] 284 1 T119 4 T182 7 T183 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 456 1 T119 8 T182 15 T183 10
auto[1] 396 1 T119 4 T182 6 T183 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 397 1 T119 7 T182 9 T183 8
auto[1] 455 1 T119 5 T182 12 T183 13


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 514 1 T119 8 T182 13 T183 9
auto[1] 338 1 T119 4 T182 8 T183 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 63 1 T119 1 T182 2 T183 4
all_values[0] auto[0] auto[0] auto[1] 20 1 T119 1 T182 1 T184 1
all_values[0] auto[0] auto[1] auto[0] 52 1 T119 1 T182 1 T185 2
all_values[0] auto[0] auto[1] auto[1] 36 1 T186 1 T159 1 T187 3
all_values[0] auto[1] auto[0] auto[1] 62 1 T119 1 T182 2 T183 1
all_values[0] auto[1] auto[1] auto[1] 51 1 T182 1 T183 2 T185 1
all_values[1] auto[0] auto[0] auto[0] 81 1 T119 1 T182 3 T183 1
all_values[1] auto[0] auto[1] auto[0] 80 1 T119 2 T182 1 T185 3
all_values[1] auto[1] auto[0] auto[1] 63 1 T119 1 T183 3 T158 1
all_values[1] auto[1] auto[1] auto[1] 60 1 T182 3 T183 3 T185 2
all_values[2] auto[0] auto[0] auto[0] 70 1 T119 1 T182 2 T185 1
all_values[2] auto[0] auto[0] auto[1] 31 1 T182 3 T185 1 T186 1
all_values[2] auto[0] auto[1] auto[0] 51 1 T119 1 T183 3 T185 1
all_values[2] auto[0] auto[1] auto[1] 30 1 T183 1 T159 2 T188 1
all_values[2] auto[1] auto[0] auto[1] 66 1 T119 2 T182 2 T183 1
all_values[2] auto[1] auto[1] auto[1] 36 1 T183 2 T185 3 T158 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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