Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100395022	1			T1	5878		T2	289		T4	15
all_values[1]	100395022	1			T1	5878		T2	289		T4	15
all_values[2]	100395022	1			T1	5878		T2	289		T4	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

562535

1

T1

603

T2

9

T4

30

auto[1]

300622531

1

T1

17031

T2

858

T4

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299652480

1

T1

17475

T2

828

T4

45

auto[1]

1532586

1

T1

159

T2

39

T13

480

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	164147	1			T1	405		T4	15		T13	243
all_values[0]	auto[0]	auto[1]	2143	1			T1	4		T13	2		T16	8
all_values[0]	auto[1]	auto[0]	99720013	1			T1	5420		T2	276		T13	15314
all_values[0]	auto[1]	auto[1]	508719	1			T1	49		T2	13		T13	158
all_values[1]	auto[0]	auto[0]	197647	1			T1	192		T4	15		T13	320
all_values[1]	auto[0]	auto[1]	1568	1			T1	2		T13	5		T15	7
all_values[1]	auto[1]	auto[0]	99686513	1			T1	5633		T2	276		T13	15237
all_values[1]	auto[1]	auto[1]	509294	1			T1	51		T2	13		T13	155
all_values[2]	auto[0]	auto[0]	195412	1			T2	8		T13	362		T15	12
all_values[2]	auto[0]	auto[1]	1618	1			T2	1		T13	4		T15	3
all_values[2]	auto[1]	auto[0]	99688748	1			T1	5825		T2	268		T4	15
all_values[2]	auto[1]	auto[1]	509244	1			T1	53		T2	12		T13	156