Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
375748 |
1 |
|
|
T1 |
132 |
|
T2 |
18 |
|
T4 |
2 |
auto[1] |
318140 |
1 |
|
|
T13 |
102 |
|
T17 |
162 |
|
T18 |
340 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173701 |
1 |
|
|
T1 |
24 |
|
T13 |
58 |
|
T14 |
20 |
lower_val |
172846 |
1 |
|
|
T1 |
37 |
|
T2 |
10 |
|
T13 |
46 |
zero_val |
1856 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347090 |
1 |
|
|
T1 |
64 |
|
T2 |
10 |
|
T4 |
2 |
lower_val |
346782 |
1 |
|
|
T1 |
68 |
|
T2 |
8 |
|
T13 |
116 |
zero_val |
16 |
1 |
|
|
T155 |
2 |
|
T156 |
2 |
|
T157 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47008 |
1 |
|
|
T1 |
9 |
|
T13 |
19 |
|
T14 |
7 |
higher_val |
higher_val |
auto[1] |
39761 |
1 |
|
|
T13 |
5 |
|
T17 |
19 |
|
T18 |
44 |
higher_val |
lower_val |
auto[0] |
47171 |
1 |
|
|
T1 |
15 |
|
T13 |
19 |
|
T14 |
13 |
higher_val |
lower_val |
auto[1] |
39757 |
1 |
|
|
T13 |
15 |
|
T17 |
28 |
|
T18 |
37 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T158 |
2 |
|
T159 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T160 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
46868 |
1 |
|
|
T1 |
20 |
|
T2 |
6 |
|
T13 |
16 |
lower_val |
higher_val |
auto[1] |
39675 |
1 |
|
|
T13 |
10 |
|
T17 |
24 |
|
T18 |
41 |
lower_val |
lower_val |
auto[0] |
46359 |
1 |
|
|
T1 |
17 |
|
T2 |
4 |
|
T13 |
10 |
lower_val |
lower_val |
auto[1] |
39939 |
1 |
|
|
T13 |
10 |
|
T17 |
14 |
|
T18 |
44 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T159 |
1 |
|
T161 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T156 |
1 |
|
T157 |
1 |
|
T162 |
1 |
zero_val |
higher_val |
auto[0] |
694 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
235 |
1 |
|
|
T13 |
2 |
|
T18 |
2 |
|
T163 |
2 |
zero_val |
lower_val |
auto[0] |
703 |
1 |
|
|
T2 |
1 |
|
T13 |
1 |
|
T5 |
1 |
zero_val |
lower_val |
auto[1] |
224 |
1 |
|
|
T13 |
1 |
|
T18 |
3 |
|
T163 |
2 |