Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100395022	1			T1	5878		T2	289		T4	15
all_pins[1]	100395022	1			T1	5878		T2	289		T4	15
all_pins[2]	100395022	1			T1	5878		T2	289		T4	15

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300391463	1			T1	17585		T2	854		T4	45
values[0x1]	793603	1			T1	49		T2	13		T13	1398
transitions[0x0=>0x1]	791856	1			T1	49		T2	13		T13	1391
transitions[0x1=>0x0]	791878	1			T1	49		T2	13		T13	1391

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99886303	1			T1	5829		T2	276		T4	15
all_pins[0]	values[0x1]	508719	1			T1	49		T2	13		T13	158
all_pins[0]	transitions[0x0=>0x1]	508705	1			T1	49		T2	13		T13	158
all_pins[0]	transitions[0x1=>0x0]	53	1			T62	3		T167	3		T168	5
all_pins[1]	values[0x0]	100394955	1			T1	5878		T2	289		T4	15
all_pins[1]	values[0x1]	67	1			T62	3		T167	3		T168	5
all_pins[1]	transitions[0x0=>0x1]	53	1			T62	3		T167	3		T168	5
all_pins[1]	transitions[0x1=>0x0]	284803	1			T13	1240		T14	327		T18	6886
all_pins[2]	values[0x0]	100110205	1			T1	5878		T2	289		T4	15
all_pins[2]	values[0x1]	284817	1			T13	1240		T14	327		T18	6886
all_pins[2]	transitions[0x0=>0x1]	283098	1			T13	1233		T14	326		T18	6841
all_pins[2]	transitions[0x1=>0x0]	507022	1			T1	49		T2	13		T13	151