Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	684	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5507	1			T1	6		T13	4		T14	12
len_601_800	12521	1			T1	16		T13	21		T14	15
len_401_600	8180	1			T1	7		T13	14		T14	9
len_201_400	16450	1			T1	4		T13	6		T14	6
len_65_200	73865	1			T1	1		T13	22		T14	2
len_min_for_xof_require_squeeze	1012	1			T76	10		T163	9		T78	10
len_keccak_block_sizes[72]	758	1			T18	1		T76	5		T163	9
len_keccak_block_sizes[104]	757	1			T17	2		T76	5		T163	9
len_keccak_block_sizes[136]	754	1			T18	1		T76	5		T163	9
len_keccak_block_sizes[144]	277	1			T17	1		T76	5		T78	5
len_keccak_block_sizes[168]	293	1			T14	1		T76	5		T22	1
len_datapath_width	14154	1			T1	1		T2	3		T13	8
len_2_63	214338	1			T1	31		T2	6		T13	41
len_1	47	1			T18	1		T39	1		T183	1