Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10727464 |
1 |
|
|
T1 |
7080 |
|
T2 |
96 |
|
T13 |
9973 |
auto[1] |
25719232 |
1 |
|
|
T1 |
10838 |
|
T2 |
450 |
|
T13 |
15772 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36327343 |
1 |
|
|
T1 |
17891 |
|
T2 |
546 |
|
T13 |
25681 |
triple_byte_access |
39664 |
1 |
|
|
T1 |
13 |
|
T13 |
25 |
|
T14 |
12 |
halfword_access |
40130 |
1 |
|
|
T1 |
8 |
|
T13 |
20 |
|
T14 |
12 |
byte_access |
39559 |
1 |
|
|
T1 |
6 |
|
T13 |
19 |
|
T14 |
16 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10608111 |
1 |
|
|
T1 |
7053 |
|
T2 |
96 |
|
T13 |
9909 |
auto[0] |
triple_byte_access |
39664 |
1 |
|
|
T1 |
13 |
|
T13 |
25 |
|
T14 |
12 |
auto[0] |
halfword_access |
40130 |
1 |
|
|
T1 |
8 |
|
T13 |
20 |
|
T14 |
12 |
auto[0] |
byte_access |
39559 |
1 |
|
|
T1 |
6 |
|
T13 |
19 |
|
T14 |
16 |
auto[1] |
word_access |
25719232 |
1 |
|
|
T1 |
10838 |
|
T2 |
450 |
|
T13 |
15772 |