Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101125725	1			T1	459941		T2	271		T3	325
all_values[1]	101125725	1			T1	459941		T2	271		T3	325
all_values[2]	101125725	1			T1	459941		T2	271		T3	325

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

542817

1

T1

38

T3

186

T13

22

auto[1]

302834358

1

T1

137978

T2

813

T3

789

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301837077

1

T1

136968

T2

771

T3

930

auto[1]

1540098

1

T1

10134

T2

42

T3

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	198001	1			T1	17		T3	77		T13	6
all_values[0]	auto[0]	auto[1]	2097	1			T1	14		T3	6		T13	2
all_values[0]	auto[1]	auto[0]	100414358	1			T1	456546		T2	257		T3	233
all_values[0]	auto[1]	auto[1]	511269	1			T1	3364		T2	14		T3	9
all_values[1]	auto[0]	auto[0]	161455	1			T3	4		T16	89		T4	14
all_values[1]	auto[0]	auto[1]	1400	1			T3	2		T16	2		T19	3
all_values[1]	auto[1]	auto[0]	100450904	1			T1	456563		T2	257		T3	306
all_values[1]	auto[1]	auto[1]	511966	1			T1	3378		T2	14		T3	13
all_values[2]	auto[0]	auto[0]	178203	1			T1	3		T3	89		T13	11
all_values[2]	auto[0]	auto[1]	1661	1			T1	4		T3	8		T13	3
all_values[2]	auto[1]	auto[0]	100434156	1			T1	456560		T2	257		T3	221
all_values[2]	auto[1]	auto[1]	511705	1			T1	3374		T2	14		T3	7