Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
353034 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
2 |
auto[1] |
345304 |
1 |
|
|
T1 |
4528 |
|
T3 |
16 |
|
T15 |
156 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175922 |
1 |
|
|
T1 |
1097 |
|
T3 |
6 |
|
T15 |
44 |
lower_val |
172079 |
1 |
|
|
T1 |
1096 |
|
T2 |
6 |
|
T3 |
5 |
zero_val |
1876 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350148 |
1 |
|
|
T1 |
2294 |
|
T2 |
8 |
|
T3 |
8 |
lower_val |
348172 |
1 |
|
|
T1 |
2236 |
|
T2 |
10 |
|
T3 |
10 |
zero_val |
18 |
1 |
|
|
T169 |
2 |
|
T170 |
2 |
|
T171 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44648 |
1 |
|
|
T18 |
7 |
|
T19 |
599 |
|
T64 |
71 |
higher_val |
higher_val |
auto[1] |
43459 |
1 |
|
|
T1 |
585 |
|
T3 |
2 |
|
T15 |
25 |
higher_val |
lower_val |
auto[0] |
44319 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
higher_val |
lower_val |
auto[1] |
43492 |
1 |
|
|
T1 |
511 |
|
T3 |
3 |
|
T15 |
19 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T172 |
1 |
|
T173 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T174 |
2 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
43613 |
1 |
|
|
T2 |
2 |
|
T13 |
4 |
|
T18 |
5 |
lower_val |
higher_val |
auto[1] |
42710 |
1 |
|
|
T1 |
562 |
|
T3 |
4 |
|
T15 |
21 |
lower_val |
lower_val |
auto[0] |
43024 |
1 |
|
|
T2 |
4 |
|
T13 |
2 |
|
T18 |
5 |
lower_val |
lower_val |
auto[1] |
42729 |
1 |
|
|
T1 |
534 |
|
T3 |
1 |
|
T15 |
14 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T171 |
1 |
|
T175 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T176 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
706 |
1 |
|
|
T15 |
1 |
|
T18 |
1 |
|
T19 |
4 |
zero_val |
higher_val |
auto[1] |
253 |
1 |
|
|
T1 |
3 |
|
T17 |
6 |
|
T39 |
1 |
zero_val |
lower_val |
auto[0] |
686 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
231 |
1 |
|
|
T1 |
3 |
|
T16 |
2 |
|
T17 |
4 |