Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
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Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 10351 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 9138 1 T1 38 T17 30 T19 30
len_5001_7500 14781 1 T1 36 T17 30 T19 30
len_2501_5000 9343 1 T1 36 T17 30 T19 30
len_1025_2500 5481 1 T1 22 T17 16 T19 16
len_769_1024 6171 1 T1 4 T15 8 T16 27
len_513_768 6571 1 T1 4 T15 13 T16 26
len_257_512 21219 1 T1 52 T15 14 T16 31
len_0_256 259388 1 T1 2017 T2 9 T3 9
len_keccak_block_sizes[72] 723 1 T1 3 T17 3 T19 3
len_keccak_block_sizes[104] 629 1 T1 3 T15 1 T17 3
len_keccak_block_sizes[136] 531 1 T1 3 T16 1 T17 3
len_keccak_block_sizes[144] 417 1 T1 3 T17 3 T19 3
len_keccak_block_sizes[168] 324 1 T1 3 T17 3 T19 3
len_1 753 1 T1 3 T17 3 T19 3
len_0 1205 1 T1 3 T17 3 T19 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%