Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101125725	1			T1	459941		T2	271		T3	325
all_pins[1]	101125725	1			T1	459941		T2	271		T3	325
all_pins[2]	101125725	1			T1	459941		T2	271		T3	325

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302567770	1			T1	137645		T2	799		T3	966
values[0x1]	809405	1			T1	3364		T2	14		T3	9
transitions[0x0=>0x1]	807539	1			T1	3364		T2	14		T3	9
transitions[0x1=>0x0]	807567	1			T1	3364		T2	14		T3	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100614456	1			T1	456577		T2	257		T3	316
all_pins[0]	values[0x1]	511269	1			T1	3364		T2	14		T3	9
all_pins[0]	transitions[0x0=>0x1]	511264	1			T1	3364		T2	14		T3	9
all_pins[0]	transitions[0x1=>0x0]	80	1			T45	3		T182	6		T132	4
all_pins[1]	values[0x0]	101125640	1			T1	459941		T2	271		T3	325
all_pins[1]	values[0x1]	85	1			T45	3		T182	6		T132	4
all_pins[1]	transitions[0x0=>0x1]	76	1			T45	3		T182	6		T132	4
all_pins[1]	transitions[0x1=>0x0]	298042	1			T24	4562		T25	2144		T48	223
all_pins[2]	values[0x0]	100827674	1			T1	459941		T2	271		T3	325
all_pins[2]	values[0x1]	298051	1			T24	4562		T25	2144		T48	223
all_pins[2]	transitions[0x0=>0x1]	296199	1			T24	4533		T25	2131		T48	223
all_pins[2]	transitions[0x1=>0x0]	509445	1			T1	3364		T2	14		T3	9