Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342759 |
1 |
|
|
T1 |
2193 |
|
T2 |
8 |
|
T3 |
9 |
auto[1] |
3238 |
1 |
|
|
T15 |
14 |
|
T16 |
28 |
|
T18 |
4 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
307004 |
1 |
|
|
T1 |
2193 |
|
T15 |
57 |
|
T16 |
100 |
auto[1] |
38993 |
1 |
|
|
T2 |
8 |
|
T3 |
9 |
|
T13 |
9 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332088 |
1 |
|
|
T1 |
2193 |
|
T2 |
8 |
|
T3 |
9 |
auto[1] |
13909 |
1 |
|
|
T15 |
27 |
|
T16 |
58 |
|
T18 |
5 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13909 |
1 |
|
|
T15 |
27 |
|
T16 |
58 |
|
T18 |
5 |
sw_kmac_invalid_sideload |
332088 |
1 |
|
|
T1 |
2193 |
|
T2 |
8 |
|
T3 |
9 |
app_valid_sideload |
13909 |
1 |
|
|
T15 |
27 |
|
T16 |
58 |
|
T18 |
5 |
app_invalid_sideload |
332088 |
1 |
|
|
T1 |
2193 |
|
T2 |
8 |
|
T3 |
9 |