Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101159633	1			T1	567553		T2	303		T4	228697
all_values[1]	101159633	1			T1	567553		T2	303		T4	228697
all_values[2]	101159633	1			T1	567553		T2	303		T4	228697

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

607497

1

T1

11

T4

19

T12

34

auto[1]

302871402

1

T1

170264

T2

909

T4

686072

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301927452

1

T1

169202

T2

876

T4

684309

auto[1]

1551447

1

T1

10635

T2

33

T4

1782

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	214075	1			T12	5		T13	9278		T14	1
all_values[0]	auto[0]	auto[1]	2235	1			T12	6		T13	22		T14	2
all_values[0]	auto[1]	auto[0]	100428409	1			T1	564008		T2	292		T4	228103
all_values[0]	auto[1]	auto[1]	514914	1			T1	3545		T2	11		T4	594
all_values[1]	auto[0]	auto[0]	186072	1			T4	5		T12	3		T13	2191
all_values[1]	auto[0]	auto[1]	1663	1			T4	2		T12	4		T13	17
all_values[1]	auto[1]	auto[0]	100456412	1			T1	564008		T2	292		T4	228098
all_values[1]	auto[1]	auto[1]	515486	1			T1	3545		T2	11		T4	592
all_values[2]	auto[0]	auto[0]	201791	1			T1	7		T4	8		T12	9
all_values[2]	auto[0]	auto[1]	1661	1			T1	4		T4	4		T12	7
all_values[2]	auto[1]	auto[0]	100440693	1			T1	564001		T2	292		T4	228095
all_values[2]	auto[1]	auto[1]	515488	1			T1	3541		T2	11		T4	590