Summary for Variable key_len
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for key_len
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Key128] |
67238 |
1 |
|
|
T1 |
499 |
|
T4 |
76 |
|
T12 |
47 |
auto[Key192] |
66607 |
1 |
|
|
T1 |
466 |
|
T4 |
82 |
|
T12 |
39 |
auto[Key256] |
84800 |
1 |
|
|
T1 |
461 |
|
T2 |
9 |
|
T4 |
89 |
auto[Key384] |
66046 |
1 |
|
|
T1 |
418 |
|
T4 |
73 |
|
T12 |
54 |
auto[Key512] |
66482 |
1 |
|
|
T1 |
493 |
|
T4 |
70 |
|
T12 |
58 |
Summary for Variable kmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
313570 |
1 |
|
|
T1 |
2337 |
|
T4 |
390 |
|
T12 |
246 |
auto[1] |
37603 |
1 |
|
|
T2 |
9 |
|
T13 |
337 |
|
T23 |
33 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
67441 |
1 |
|
|
T4 |
390 |
|
T12 |
246 |
|
T13 |
12 |
auto[Shake] |
242456 |
1 |
|
|
T1 |
2337 |
|
T13 |
123 |
|
T14 |
2337 |
auto[CShake] |
41276 |
1 |
|
|
T2 |
9 |
|
T13 |
378 |
|
T23 |
34 |
Summary for Variable msg_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for msg_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175316 |
1 |
|
|
T1 |
1196 |
|
T2 |
4 |
|
T4 |
203 |
auto[1] |
175857 |
1 |
|
|
T1 |
1141 |
|
T2 |
5 |
|
T4 |
187 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339150 |
1 |
|
|
T1 |
2337 |
|
T2 |
9 |
|
T4 |
390 |
auto[1] |
12023 |
1 |
|
|
T13 |
134 |
|
T23 |
10 |
|
T24 |
23 |
Summary for Variable state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175898 |
1 |
|
|
T1 |
1172 |
|
T2 |
4 |
|
T4 |
204 |
auto[1] |
175275 |
1 |
|
|
T1 |
1165 |
|
T2 |
5 |
|
T4 |
186 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
141895 |
1 |
|
|
T1 |
2337 |
|
T2 |
6 |
|
T13 |
240 |
auto[L224] |
19868 |
1 |
|
|
T4 |
390 |
|
T13 |
4 |
|
T15 |
390 |
auto[L256] |
160886 |
1 |
|
|
T2 |
3 |
|
T13 |
262 |
|
T16 |
374 |
auto[L384] |
15867 |
1 |
|
|
T13 |
4 |
|
T23 |
1 |
|
T41 |
2 |
auto[L512] |
12657 |
1 |
|
|
T12 |
246 |
|
T13 |
3 |
|
T69 |
2 |
Summary for Variable xof_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for xof_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329807 |
1 |
|
|
T1 |
2337 |
|
T2 |
9 |
|
T4 |
390 |
auto[1] |
21366 |
1 |
|
|
T13 |
199 |
|
T23 |
21 |
|
T41 |
13 |
Summary for Cross kmac_cross
Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for kmac_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
37603 |
1 |
|
|
T2 |
9 |
|
T13 |
337 |
|
T23 |
33 |
Summary for Cross cshake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for cshake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
41276 |
1 |
|
|
T2 |
9 |
|
T13 |
378 |
|
T23 |
34 |
Summary for Cross shake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for shake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
242456 |
1 |
|
|
T1 |
2337 |
|
T13 |
123 |
|
T14 |
2337 |
Summary for Cross sha3_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for sha3_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
67441 |
1 |
|
|
T4 |
390 |
|
T12 |
246 |
|
T13 |
12 |